riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/docs/source/code_examples/show/cmos.v

4 lines
74 B
Verilog
Raw Permalink Blame History

module cmos_demo(input a, b, output [1:0] y);
assign y = a + b;
endmodule
Reference in New Issue View Git Blame Copy Permalink