read_verilog <> (w * (3'b110)); endmodule EOT prep -nokeepdc equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### design -reset read_verilog <> (S*3); endmodule EOT prep design -save gold peepopt design -stash gate design -import gold -as gold peepopt_shiftmul_2 design -import gate -as gate peepopt_shiftmul_2 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter sat -verify -show-public -enable_undef -prove-asserts miter cd gate select -assert-count 1 t:$shr select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### design -reset read_verilog <> (S*5); endmodule EOT prep design -save gold peepopt design -stash gate design -import gold -as gold peepopt_shiftmul_3 design -import gate -as gate peepopt_shiftmul_3 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter sat -verify -show-public -enable_undef -prove-asserts miter cd gate select -assert-count 1 t:$shr select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### design -reset read_verilog <