# read read_verilog counter.v hierarchy -check -top counter show -notitle -format dot -prefix counter_00 # elaborate proc show -notitle -format dot -prefix counter_proc opt show -notitle -format dot -prefix counter_01 # mapping to internal cell library techmap; opt splitnets -ports;; show -notitle -format dot -prefix counter_02 # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib # mapping logic to mycells.lib abc -liberty mycells.lib # cleanup clean show -notitle -lib mycells.v -format dot -prefix counter_03