read_verilog macc.v
proc
hierarchy -top top
#Failed because of 14 unproven cells.
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
#equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 4 t:CCU2C
select -assert-count 6 t:L6MUX21
select -assert-count 49 t:LUT4
select -assert-count 19 t:PFUMX
select -assert-count 7 t:TRELLIS_FF

select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX  t:TRELLIS_FF %% t:* %D