read_verilog alu.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module


select -assert-count 1 t:BUFG
select -assert-count 32 t:LUT1
select -assert-count 142 t:LUT2
select -assert-count 55  t:LUT3
select -assert-count 70  t:LUT4
select -assert-count 46  t:LUT5
select -assert-count 625 t:LUT6
select -assert-count 62 t:MUXCY
select -assert-count 265  t:MUXF7
select -assert-count 79  t:MUXF8
select -assert-count 64 t:XORCY
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D