read_verilog ../common/fsm.v hierarchy -top fsm proc flatten equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module select -assert-max 16 t:LUT4 select -assert-count 6 t:TRELLIS_FF select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D