read_verilog ../common/fsm.v hierarchy -top fsm proc flatten equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore async2sync miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module select -assert-count 6 t:NX_DFF select -assert-count 13 t:NX_LUT select -assert-none t:NX_DFF t:NX_LUT %% t:* %D