read_verilog ../common/dffs.v
design -save read

hierarchy -top dff
proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D

design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D