$date
  Fri Sep 27 11:58:46 2024
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module tb $end
$var reg 4 ! a[3:0] $end
$var reg 4 " b[3:0] $end
$scope module uut $end
$var reg 4 # a[3:0] $end
$var reg 4 $ b[3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b0001 !
b0001 "
b0001 #
b0001 $
#10000000