read_verilog <<EOT (* techmap_celltype = "$_DFF_P_" *) module ffmap(...); input D; input C; output Q; parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C)); wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule EOT design -stash map read_verilog <<EOT (* techmap_celltype = "$_DFF_P_" *) module ffmap(...); input D; input C; output Q; parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx; ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C)); wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1; wire _TECHMAP_REMOVEINIT_Q_ = 1'b0; endmodule EOT design -stash map_noremove read_verilog <<EOT module ffbb (...); parameter [0:0] INIT = 1'bx; input D, C; output Q; endmodule module top(...); input clk; input d; output reg q0 = 0; output reg q1 = 1; output reg qq0 = 0; output reg qx; always @(posedge clk) begin q0 <= d; q1 <= d; qq0 <= q0; qx <= d; end endmodule EOT design -save ref hierarchy -auto-top proc simplemap techmap -map %map clean # Make sure the parameter was used properly. select -assert-count 3 top/t:ffbb select -set ff0 top/w:q0 %ci t:ffbb %i select -set ffq0 top/w:qq0 %ci t:ffbb %i select -set ffx top/w:qx %ci t:ffbb %i select -assert-count 1 @ff0 select -assert-count 1 @ffq0 select -assert-count 1 @ffx select -assert-count 1 @ff0 r:INIT=1'b0 %i select -assert-count 1 @ffq0 r:INIT=1'b0 %i select -assert-count 1 @ffx r:INIT=1'bx %i select -assert-count 0 top/w:q1 %ci t:ffbb %i # Make sure the init values are dropped from the wires iff mapping was performed. select -assert-count 0 top/w:q0 a:init %i select -assert-count 0 top/w:qq0 a:init %i select -assert-count 1 top/w:q1 a:init=1'b1 %i select -assert-count 0 top/w:qx a:init %i design -load ref hierarchy -auto-top proc simplemap techmap -map %map_noremove clean # Make sure the parameter was used properly. select -assert-count 3 top/t:ffbb select -set ff0 top/w:q0 %ci t:ffbb %i select -set ffq0 top/w:qq0 %ci t:ffbb %i select -set ffx top/w:qx %ci t:ffbb %i select -assert-count 1 @ff0 select -assert-count 1 @ffq0 select -assert-count 1 @ffx select -assert-count 1 @ff0 r:INIT=1'b0 %i select -assert-count 1 @ffq0 r:INIT=1'b0 %i select -assert-count 1 @ffx r:INIT=1'bx %i select -assert-count 0 top/w:q1 %ci t:ffbb %i # Make sure the init values are not dropped from the wires. select -assert-count 1 top/w:q0 a:init=1'b0 %i select -assert-count 1 top/w:qq0 a:init=1'b0 %i select -assert-count 1 top/w:q1 a:init=1'b1 %i select -assert-count 0 top/w:qx a:init %i