read_verilog latches.v
design -save read

proc
async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
flatten
synth_xilinx
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

design -load read

synth_xilinx
flatten
cd top
select -assert-count 1 t:LUT1
select -assert-count 2 t:LUT3
#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
select -assert-count 3 t:$_DLATCH_P_
select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D