read_verilog fsm.v
hierarchy -top fsm
proc
flatten
#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module

select -assert-count 1  t:EFX_GBUFCE
select -assert-count 6  t:EFX_FF
select -assert-count 15 t:EFX_LUT4
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D