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riscv:main
riscv:krys/reduce_warnings
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riscv:setenv_pass
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riscv:hierarchy_notify_top_attr
riscv:dlfcn-submodule
riscv:emil/fix-filterlib-roundtrip
riscv:ql_noflatten_option
riscv:emil/path-sep-refactor
riscv:docs-preview-cmdref_groups
riscv:emil/idstring-in-fold
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riscv:micko/ci_functional
riscv:emil/prove-hash-sensitivity
riscv:emil/fix-fsmdata-insertion
riscv:emil/proc_dff-rule-order
riscv:aiju/docs_gvpack_fix
riscv:emil/nix-cross-compile
riscv:krys/quotes
riscv:emil/src-attribute-std-string
riscv:emil/proc_rom-src-test
riscv:emil/main-nohash
riscv:emil/sigspec-union-nohash
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riscv:krys/abc-safe
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riscv:emil/sigspec-union
riscv:emil/sigspec-hell
riscv:emil/cell-playground-3
riscv:lofty/remove-sorts
riscv:emil/special-src-attribute
riscv:emil/tag-dict-inherit
riscv:emil/small-astnode
riscv:emil/nix-brokey
riscv:emil/cell-playground
riscv:krys/fix-4427
riscv:emil/tracy
riscv:emil/bufnorm-notes
riscv:update_flake_lock_action
riscv:ywb_asserts
riscv:emil/nix
riscv:lofty/intel_alm-memory_libmap
riscv:mmicko/orig_params
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riscv:ecp5_2_lattice
riscv:lofty/abc9-by-default
riscv:efb
riscv:nexus_2_lattice
riscv:claire/toposort
riscv:mmicko/verific
riscv:aki/clang_tidy
riscv:aki/wire_limit
riscv:jix/witness_flow
riscv:lofty/abc9-output-conflict
riscv:claire/ipc
riscv:claire/fix2728
riscv:sanitizers
riscv:verific-improvements
riscv:eddie/clean_unused_init
riscv:eddie/sta
riscv:eddie/ecp5_init
riscv:eddie/fix1649
riscv:0.47
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riscv:yosys-0.43
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riscv:yosys-0.37
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riscv:yosys-0.35
riscv:yosys-0.34
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riscv:yosys-0.2.0

10 Commits
e67c3706eb ... c9645fbabe

Author SHA1 Message Date
George Rennie c9645fbabe
Merge d7c6688905 into 6f3376cbe6 2024-11-29 12:20:36 +03:30
KrystalDelusion 6f3376cbe6
Merge pull request #4730 from YosysHQ/krys/downstream-docs 
Improvements for downstream-distro maintainability.
 2024-11-28 14:35:16 +13:00
github-actions[bot] 87742fa688 Bump version 2024-11-28 01:26:26 +00:00
Martin Povišer 646c5a19a8
Merge pull request #4776 from YosysHQ/krys/get_blackbox_attribute 
Move get_blackbox_attribute method to Module instead of AttrObject
 2024-11-28 00:25:16 +01:00
KrystalDelusion f428163252
Move get_blackbox_attribute method to Module instead of AttrObject 2024-11-28 11:19:16 +13:00
Krystine Sherwin e649c1a8e1
Docs: Accept empty string for release envvar 2024-11-20 12:31:12 +13:00
Krystine Sherwin 44b68fb498
Docs: Add check for envvar to disable todos 2024-11-20 12:18:17 +13:00
George Rennie d7c6688905 write_btor: support $_BUF_ 2024-11-15 11:47:09 +01:00
Krystine Sherwin 1476eaba00
Docs: Add fallback for missing furo_ys 
This is mainly intended for (latex)pdf builds which do not use the furo-ys html theme, where the yosys script syntax highlighting can safely fallback to plaintext.  This effectively makes `furo-ys` an optional dependency to simplify distro-package maintainability.
See also #4725.
 2024-11-12 16:23:12 +13:00
George Rennie 9047290683 write_btor: support $buf 
* treated the same as $pos
 2024-11-06 19:49:09 +01:00
4 changed files with 18 additions and 6 deletions
Show Stats Expand all files Collapse all files

2
Makefile
View File

@ -155,7 +155,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE CXXFLAGS += -D_DEFAULT_SOURCE
endif endif
YOSYS_VER := 0.47+121 YOSYS_VER := 0.47+135
# Note: We arrange for .gitcommit to contain the (short) commit hash in # Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo # tarballs generated with git-archive(1) using .gitattributes. The git repo

6
backends/btor/btor.cc
View File

@ -508,7 +508,7 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos))) if (cell->type.in(ID($not), ID($neg), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
{ {
string btor_op; string btor_op;
if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not"; if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
@ -520,9 +520,9 @@ struct BtorWorker
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
SigSpec sig = sigmap(cell->getPort(ID::Y)); SigSpec sig = sigmap(cell->getPort(ID::Y));
// the $pos cell just passes through, all other cells need an actual operation applied // the $pos/$buf cells just pass through, all other cells need an actual operation applied
int nid = nid_a; int nid = nid_a;
if (cell->type != ID($pos)) if (!cell->type.in(ID($pos), ID($buf), ID($_BUF_)))
{ {
log_assert(!btor_op.empty()); log_assert(!btor_op.empty());
int sid = get_bv_sid(width); int sid = get_bv_sid(width);

11
docs/source/conf.py
View File

@ -56,6 +56,9 @@ if os.getenv("READTHEDOCS"):
else: else:
release = yosys_ver release = yosys_ver
todo_include_todos = False todo_include_todos = False
elif os.getenv("YOSYS_DOCS_RELEASE") is not None:
release = yosys_ver
todo_include_todos = False
else: else:
release = yosys_ver release = yosys_ver
todo_include_todos = True todo_include_todos = True
@ -87,5 +90,9 @@ def setup(app: Sphinx) -> None:
from util.RtlilLexer import RtlilLexer from util.RtlilLexer import RtlilLexer
app.add_lexer("RTLIL", RtlilLexer) app.add_lexer("RTLIL", RtlilLexer)
from furo_ys.lexers.YoscryptLexer import YoscryptLexer try:
app.add_lexer("yoscrypt", YoscryptLexer) from furo_ys.lexers.YoscryptLexer import YoscryptLexer
app.add_lexer("yoscrypt", YoscryptLexer)
except ModuleNotFoundError:
from pygments.lexers.special import TextLexer
app.add_lexer("yoscrypt", TextLexer)

5
kernel/rtlil.h
View File

@ -814,6 +814,7 @@ struct RTLIL::AttrObject
void set_bool_attribute(const RTLIL::IdString &id, bool value=true); void set_bool_attribute(const RTLIL::IdString &id, bool value=true);
bool get_bool_attribute(const RTLIL::IdString &id) const; bool get_bool_attribute(const RTLIL::IdString &id) const;
[[deprecated("Use Module::get_blackbox_attribute() instead.")]]
bool get_blackbox_attribute(bool ignore_wb=false) const { bool get_blackbox_attribute(bool ignore_wb=false) const {
return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox)); return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));
} }
@ -1291,6 +1292,10 @@ public:
virtual void optimize(); virtual void optimize();
virtual void makeblackbox(); virtual void makeblackbox();
bool get_blackbox_attribute(bool ignore_wb=false) const {
return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));
}
void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
void new_connections(const std::vector<RTLIL::SigSig> &new_conn); void new_connections(const std::vector<RTLIL::SigSig> &new_conn);