riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Compare commits

base: riscv:cd3fe7be7970406f0292d83870256e259cef4db1
Branches Tags
riscv:krys/reduce_warnings
riscv:emil/han-carlson-adder
riscv:emil/blockrom-driver-conflict
riscv:emil/opt_expr-limit-effort
riscv:emil/make-test-faster
riscv:setenv_pass
riscv:main
riscv:docs-preview-noguidelines
riscv:krys/refactor_selections
riscv:krys/get_blackbox_attribute
riscv:emil/autoidx-option
riscv:emil/hashlib-interface
riscv:krys/blackboxes
riscv:emil/yosys-config-version
riscv:emil/clockgate-liberty
riscv:emil/opt_merge-hashing
riscv:hierarchy_notify_top_attr
riscv:dlfcn-submodule
riscv:emil/fix-filterlib-roundtrip
riscv:ql_noflatten_option
riscv:emil/path-sep-refactor
riscv:docs-preview-cmdref_groups
riscv:emil/idstring-in-fold
riscv:emil/fix-mac-lto-plugins
riscv:emil/readme-mac-lto
riscv:emil/pyosys-fix-segfault
riscv:docs-preview-cellhelp
riscv:lofty/ql-oopsie
riscv:emil/log-deprecated-temp
riscv:emil/document-perffile
riscv:micko/ci_functional
riscv:emil/prove-hash-sensitivity
riscv:emil/fix-fsmdata-insertion
riscv:emil/proc_dff-rule-order
riscv:aiju/docs_gvpack_fix
riscv:emil/nix-cross-compile
riscv:krys/quotes
riscv:emil/src-attribute-std-string
riscv:emil/proc_rom-src-test
riscv:emil/main-nohash
riscv:emil/sigspec-union-nohash
riscv:emil/swap-disposable
riscv:claire/vay
riscv:krys/abc-safe
riscv:emil/bitpattern-comments
riscv:emil/sigspec-union
riscv:emil/sigspec-hell
riscv:emil/cell-playground-3
riscv:lofty/remove-sorts
riscv:emil/special-src-attribute
riscv:emil/tag-dict-inherit
riscv:emil/small-astnode
riscv:emil/nix-brokey
riscv:emil/cell-playground
riscv:krys/fix-4427
riscv:emil/tracy
riscv:emil/bufnorm-notes
riscv:update_flake_lock_action
riscv:ywb_asserts
riscv:emil/nix
riscv:lofty/intel_alm-memory_libmap
riscv:mmicko/orig_params
riscv:krys/ql-tests
riscv:ecp5_2_lattice
riscv:lofty/abc9-by-default
riscv:efb
riscv:nexus_2_lattice
riscv:claire/toposort
riscv:mmicko/verific
riscv:aki/clang_tidy
riscv:aki/wire_limit
riscv:jix/witness_flow
riscv:lofty/abc9-output-conflict
riscv:claire/ipc
riscv:claire/fix2728
riscv:sanitizers
riscv:verific-improvements
riscv:eddie/clean_unused_init
riscv:eddie/sta
riscv:eddie/ecp5_init
riscv:eddie/fix1649
riscv:0.47
riscv:0.46
riscv:0.45
riscv:docs-previewtest
riscv:yosys-0.44
riscv:resources
riscv:yosys-0.43
riscv:yosys-0.42
riscv:yosys-0.41
riscv:yosys-0.40
riscv:yosys-0.39
riscv:yosys-0.38
riscv:yosys-0.37
riscv:yosys-0.36
riscv:yosys-0.35
riscv:yosys-0.34
riscv:yosys-0.33
riscv:yosys-0.32
riscv:yosys-0.31
riscv:yosys-0.30
riscv:yosys-0.29
riscv:yosys-0.28
riscv:yosys-0.27
riscv:yosys-0.26
riscv:yosys-0.25
riscv:yosys-0.24
riscv:yosys-0.23
riscv:yosys-0.22
riscv:yosys-0.21
riscv:yosys-0.20
riscv:yosys-0.19
riscv:yosys-0.18
riscv:yosys-0.17
riscv:yosys-0.16
riscv:yosys-0.15
riscv:yosys-0.14
riscv:yosys-0.13
riscv:yosys-0.12
riscv:yosys-0.11
riscv:yosys-0.10
riscv:yosys-0.9
riscv:yosys-0.8
riscv:yosys-0.7
riscv:yosys-0.6
riscv:yosys-0.5
riscv:yosys-0.4
riscv:yosys-0.3.0
riscv:yosys-0.2.0
...
compare: riscv:be088b17b3e0d70a0c3298831144170b540d4fba
Branches Tags
riscv:krys/reduce_warnings
riscv:emil/han-carlson-adder
riscv:emil/blockrom-driver-conflict
riscv:emil/opt_expr-limit-effort
riscv:emil/make-test-faster
riscv:setenv_pass
riscv:main
riscv:docs-preview-noguidelines
riscv:krys/refactor_selections
riscv:krys/get_blackbox_attribute
riscv:emil/autoidx-option
riscv:emil/hashlib-interface
riscv:krys/blackboxes
riscv:emil/yosys-config-version
riscv:emil/clockgate-liberty
riscv:emil/opt_merge-hashing
riscv:hierarchy_notify_top_attr
riscv:dlfcn-submodule
riscv:emil/fix-filterlib-roundtrip
riscv:ql_noflatten_option
riscv:emil/path-sep-refactor
riscv:docs-preview-cmdref_groups
riscv:emil/idstring-in-fold
riscv:emil/fix-mac-lto-plugins
riscv:emil/readme-mac-lto
riscv:emil/pyosys-fix-segfault
riscv:docs-preview-cellhelp
riscv:lofty/ql-oopsie
riscv:emil/log-deprecated-temp
riscv:emil/document-perffile
riscv:micko/ci_functional
riscv:emil/prove-hash-sensitivity
riscv:emil/fix-fsmdata-insertion
riscv:emil/proc_dff-rule-order
riscv:aiju/docs_gvpack_fix
riscv:emil/nix-cross-compile
riscv:krys/quotes
riscv:emil/src-attribute-std-string
riscv:emil/proc_rom-src-test
riscv:emil/main-nohash
riscv:emil/sigspec-union-nohash
riscv:emil/swap-disposable
riscv:claire/vay
riscv:krys/abc-safe
riscv:emil/bitpattern-comments
riscv:emil/sigspec-union
riscv:emil/sigspec-hell
riscv:emil/cell-playground-3
riscv:lofty/remove-sorts
riscv:emil/special-src-attribute
riscv:emil/tag-dict-inherit
riscv:emil/small-astnode
riscv:emil/nix-brokey
riscv:emil/cell-playground
riscv:krys/fix-4427
riscv:emil/tracy
riscv:emil/bufnorm-notes
riscv:update_flake_lock_action
riscv:ywb_asserts
riscv:emil/nix
riscv:lofty/intel_alm-memory_libmap
riscv:mmicko/orig_params
riscv:krys/ql-tests
riscv:ecp5_2_lattice
riscv:lofty/abc9-by-default
riscv:efb
riscv:nexus_2_lattice
riscv:claire/toposort
riscv:mmicko/verific
riscv:aki/clang_tidy
riscv:aki/wire_limit
riscv:jix/witness_flow
riscv:lofty/abc9-output-conflict
riscv:claire/ipc
riscv:claire/fix2728
riscv:sanitizers
riscv:verific-improvements
riscv:eddie/clean_unused_init
riscv:eddie/sta
riscv:eddie/ecp5_init
riscv:eddie/fix1649
riscv:0.47
riscv:0.46
riscv:0.45
riscv:docs-previewtest
riscv:yosys-0.44
riscv:resources
riscv:yosys-0.43
riscv:yosys-0.42
riscv:yosys-0.41
riscv:yosys-0.40
riscv:yosys-0.39
riscv:yosys-0.38
riscv:yosys-0.37
riscv:yosys-0.36
riscv:yosys-0.35
riscv:yosys-0.34
riscv:yosys-0.33
riscv:yosys-0.32
riscv:yosys-0.31
riscv:yosys-0.30
riscv:yosys-0.29
riscv:yosys-0.28
riscv:yosys-0.27
riscv:yosys-0.26
riscv:yosys-0.25
riscv:yosys-0.24
riscv:yosys-0.23
riscv:yosys-0.22
riscv:yosys-0.21
riscv:yosys-0.20
riscv:yosys-0.19
riscv:yosys-0.18
riscv:yosys-0.17
riscv:yosys-0.16
riscv:yosys-0.15
riscv:yosys-0.14
riscv:yosys-0.13
riscv:yosys-0.12
riscv:yosys-0.11
riscv:yosys-0.10
riscv:yosys-0.9
riscv:yosys-0.8
riscv:yosys-0.7
riscv:yosys-0.6
riscv:yosys-0.5
riscv:yosys-0.4
riscv:yosys-0.3.0
riscv:yosys-0.2.0

6 Commits
cd3fe7be79 ... be088b17b3

Author SHA1 Message Date
N. Engelhardt be088b17b3
Merge 96c526d1ba into 29e8812bab 2024-11-25 15:54:12 +01:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Miodrag Milanović 9512ec4bbc
Merge pull request #4764 from YosysHQ/micko/verific_vhdl_assert 
verific : VHDL assert DFF initial value set on Verific library patch
 2024-11-25 15:06:36 +01:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
N. Engelhardt 96c526d1ba Print a note about finding attribute (* top *) in hierarchy 2024-11-13 10:21:44 +01:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
3 changed files with 28 additions and 7 deletions
Show Stats Expand all files Collapse all files

7
frontends/verific/verific.cc
View File

@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log(" assert condition %s.\n", log_signal(cond));
Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
// Initialize FF feeding condition to 1, in case it is not
// used by rest of design logic, to prevent failing on
// initial uninitialized state
if (cond.is_wire() && !cond.wire->name.isPublic())
cond.wire->attributes[ID::init] = Const(1,1);
import_attributes(cell->attributes, inst);
continue;
}
@ -3428,6 +3422,7 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1);
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
RuntimeFlags::SetVar("veri_create_empty_box", 1);
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

4
passes/hierarchy/hierarchy.cc
View File

@ -1003,8 +1003,10 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr)
for (auto mod : design->modules())
if (mod->get_bool_attribute(ID::top))
if (mod->get_bool_attribute(ID::top)) {
log("Attribute `top' found on module `%s'. Setting top module to %s.\n", log_id(mod), log_id(mod));
top_mod = mod;
}
if (top_mod == nullptr)
{

24
tests/verific/blackbox.ys Normal file
View File

@ -0,0 +1,24 @@
verific -sv -lib <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
always @(posedge clk) begin
if (PATH=="DEFAULT")
c <= a;
else
c <= b;
end
endmodule
EOF
verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF
verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL