Merge 65146e3acf into 6f3376cbe6

Improvements for downstream-distro maintainability.

.github/workflows/test-compile.yml

@@ -32,9 +32,9 @@ jobs:
           # oldest supported
           - 'clang-14'
           - 'gcc-10'
-          # newest
-          - 'clang'
-          - 'gcc'
+          # newest, make sure to update maximum standard step to match
+          - 'clang-18'
+          - 'gcc-13'
         include:
           # macOS
           - os: macos-13
@@ -72,7 +72,7 @@ jobs:
 
       # maximum standard, only on newest compilers
       - name: Build C++20
-        if: ${{ matrix.compiler == 'clang' || matrix.compiler == 'gcc'}}
+        if: ${{ matrix.compiler == 'clang-18' || matrix.compiler == 'gcc-13' }}
         shell: bash
         run: |
           make config-$CC_SHORT

Makefile

@@ -155,7 +155,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.47+121
+YOSYS_VER := 0.47+135
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

docs/source/appendix/rtlil_text.rst

@@ -242,7 +242,7 @@ Processes
 
 Declares a process, with zero or more attributes, with the given identifier in
 the enclosing module. The body of a process consists of zero or more
-assignments, exactly one switch, and zero or more syncs.
+assignments followed by zero or more switches and zero or more syncs.
 
 See :ref:`sec:rtlil_process` for an overview of processes.
 
@@ -250,7 +250,7 @@ See :ref:`sec:rtlil_process` for an overview of processes.
 
     <process>       ::= <attr-stmt>* <proc-stmt> <process-body> <proc-end-stmt>
     <proc-stmt>     ::= process <id> <eol>
-    <process-body>  ::= <assign-stmt>* <switch>? <assign-stmt>* <sync>*
+    <process-body>  ::= <assign-stmt>* <switch>* <sync>*
     <assign-stmt>   ::= assign <dest-sigspec> <src-sigspec> <eol>
     <dest-sigspec>  ::= <sigspec>
     <src-sigspec>   ::= <sigspec>
@@ -262,8 +262,8 @@ Switches
 Switches test a signal for equality against a list of cases. Each case specifies
 a comma-separated list of signals to check against. If there are no signals in
 the list, then the case is the default case. The body of a case consists of zero
-or more switches and assignments. Both switches and cases may have zero or more
-attributes.
+or more assignments followed by zero or more switches. Both switches and cases
+may have zero or more attributes.
 
 .. code:: BNF
 
@@ -272,7 +272,7 @@ attributes.
     <case>              ::= <attr-stmt>* <case-stmt> <case-body>
     <case-stmt>         ::= case <compare>? <eol>
     <compare>           ::= <sigspec> (, <sigspec>)*
-    <case-body>         ::= (<switch> | <assign-stmt>)*
+    <case-body>         ::= <assign-stmt>* <switch>*
     <switch-end-stmt>   ::= end <eol>
 
 Syncs

docs/source/conf.py

@@ -56,6 +56,9 @@ if os.getenv("READTHEDOCS"):
     else:
         release = yosys_ver
         todo_include_todos = False
+elif os.getenv("YOSYS_DOCS_RELEASE") is not None:
+    release = yosys_ver
+    todo_include_todos = False
 else:
     release = yosys_ver
     todo_include_todos = True
@@ -87,5 +90,9 @@ def setup(app: Sphinx) -> None:
     from util.RtlilLexer import RtlilLexer
     app.add_lexer("RTLIL", RtlilLexer)
 
-    from furo_ys.lexers.YoscryptLexer import YoscryptLexer
-    app.add_lexer("yoscrypt", YoscryptLexer)
+    try:
+        from furo_ys.lexers.YoscryptLexer import YoscryptLexer
+        app.add_lexer("yoscrypt", YoscryptLexer)
+    except ModuleNotFoundError:
+        from pygments.lexers.special import TextLexer
+        app.add_lexer("yoscrypt", TextLexer)

frontends/rtlil/rtlil_frontend.cc

@@ -31,6 +31,11 @@ void rtlil_frontend_yyerror(char const *s)
 	YOSYS_NAMESPACE_PREFIX log_error("Parser error in line %d: %s\n", rtlil_frontend_yyget_lineno(), s);
 }
 
+void rtlil_frontend_yywarning(char const *s)
+{
+	YOSYS_NAMESPACE_PREFIX log_warning("In line %d: %s\n", rtlil_frontend_yyget_lineno(), s);
+}
+
 YOSYS_NAMESPACE_BEGIN
 
 struct RTLILFrontend : public Frontend {

frontends/rtlil/rtlil_frontend.h

@@ -42,6 +42,7 @@ YOSYS_NAMESPACE_END
 extern int rtlil_frontend_yydebug;
 int rtlil_frontend_yylex(void);
 void rtlil_frontend_yyerror(char const *s);
+void rtlil_frontend_yywarning(char const *s);
 void rtlil_frontend_yyrestart(FILE *f);
 int rtlil_frontend_yyparse(void);
 int rtlil_frontend_yylex_destroy(void);

frontends/rtlil/rtlil_parser.y

@@ -344,6 +344,16 @@ assign_stmt:
 	TOK_ASSIGN sigspec sigspec EOL {
 		if (attrbuf.size() != 0)
 			rtlil_frontend_yyerror("dangling attribute");
+
+		// See https://github.com/YosysHQ/yosys/pull/4765 for discussion on this
+		// warning
+		if (!switch_stack.back()->empty()) {
+			rtlil_frontend_yywarning(
+				"case rule assign statements after switch statements may cause unexpected behaviour. "
+				"The assign statement is reordered to come before all switch statements."
+			);
+		}
+
 		case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
 		delete $2;
 		delete $3;

kernel/drivertools.h

@@ -364,7 +364,7 @@ public:
 
 	unsigned int hash() const
 	{
-		unsigned int inner;
+		unsigned int inner = 0;
 		switch (type_)
 		{
 			case DriveType::NONE:
@@ -385,6 +385,9 @@ public:
 			case DriveType::MULTIPLE:
 				inner = multiple_.hash();
 				break;
+			default:
+				log_abort();
+				break;
 		}
 		return mkhash((unsigned int)type_, inner);
 	}
@@ -912,7 +915,7 @@ public:
 
 	unsigned int hash() const
 	{
-		unsigned int inner;
+		unsigned int inner = 0;
 		switch (type_)
 		{
 			case DriveType::NONE:
@@ -933,6 +936,9 @@ public:
 			case DriveType::MULTIPLE:
 				inner = multiple_.hash();
 				break;
+			default:
+				log_abort();
+				break;
 		}
 		return mkhash((unsigned int)type_, inner);
 	}

kernel/rtlil.h

@@ -814,6 +814,7 @@ struct RTLIL::AttrObject
 	void set_bool_attribute(const RTLIL::IdString &id, bool value=true);
 	bool get_bool_attribute(const RTLIL::IdString &id) const;
 
+	[[deprecated("Use Module::get_blackbox_attribute() instead.")]]
 	bool get_blackbox_attribute(bool ignore_wb=false) const {
 		return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));
 	}
@@ -1291,6 +1292,10 @@ public:
 	virtual void optimize();
 	virtual void makeblackbox();
 
+	bool get_blackbox_attribute(bool ignore_wb=false) const {
+		return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));
+	}
+
 	void connect(const RTLIL::SigSig &conn);
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
 	void new_connections(const std::vector<RTLIL::SigSig> &new_conn);

passes/hierarchy/hierarchy.cc

@@ -1003,8 +1003,10 @@ struct HierarchyPass : public Pass {
 
 		if (top_mod == nullptr)
 			for (auto mod : design->modules())
-				if (mod->get_bool_attribute(ID::top))
+				if (mod->get_bool_attribute(ID::top)) {
+					log("Attribute `top' found on module `%s'. Setting top module to %s.\n", log_id(mod), log_id(mod));
 					top_mod = mod;
+				}
 
 		if (top_mod == nullptr)
 		{