Merge 42e4610e3a into 29e8812bab

verific: fix blackbox regression and add test case

frontends/rtlil/rtlil_parser.y

@@ -187,7 +187,11 @@ wire_stmt:
 
 wire_options:
 	wire_options TOK_WIDTH TOK_INT {
+		if ($3 > 0x1000000) {
+			rtlil_frontend_yyerror("RTLIL error: invalid wire width, must be less than 2^24");
+		} else {
 			current_wire->width = $3;
+		}
 	} |
 	wire_options TOK_WIDTH TOK_INVALID {
 		rtlil_frontend_yyerror("RTLIL error: invalid wire width");

frontends/verific/verific.cc

@@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 				log("    assert condition %s.\n", log_signal(cond));
 
 			Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
-			// Initialize FF feeding condition  to 1, in case it is not
-			// used by rest of design logic, to prevent failing on
-			// initial uninitialized state
-			if (cond.is_wire() && !cond.wire->name.isPublic())
-				cond.wire->attributes[ID::init] = Const(1,1);
-
 			import_attributes(cell->attributes, inst);
 			continue;
 		}
@@ -3428,6 +3422,7 @@ struct VerificPass : public Pass {
 			RuntimeFlags::SetVar("veri_preserve_assignments", 1);
 			RuntimeFlags::SetVar("veri_preserve_comments", 1);
 			RuntimeFlags::SetVar("veri_preserve_drivers", 1);
+			RuntimeFlags::SetVar("veri_create_empty_box", 1);
 
 			// Workaround for VIPER #13851
 			RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

kernel/rtlil.cc

@@ -216,6 +216,9 @@ std::string& Const::get_str() const {
 
 RTLIL::Const::Const(const std::string &str)
 {
+	if (str.size() * 8 > 0x1000000)
+		log_error("RTLIL Const width must be less than 2^24");
+
 	flags = RTLIL::CONST_FLAG_STRING;
 	new ((void*)&str_) std::string(str);
 	tag = backing_tag::string;
@@ -223,6 +226,12 @@ RTLIL::Const::Const(const std::string &str)
 
 RTLIL::Const::Const(long long val, int width)
 {
+	if (width < 0)
+		log_error("RTLIL Const width must not be negative");
+
+	if (width > 0x1000000)
+		log_error("RTLIL Const width must be less than 2^24");
+
 	flags = RTLIL::CONST_FLAG_NONE;
 	new ((void*)&bits_) bitvectype();
 	tag = backing_tag::bits;
@@ -236,6 +245,12 @@ RTLIL::Const::Const(long long val, int width)
 
 RTLIL::Const::Const(RTLIL::State bit, int width)
 {
+	if (width < 0)
+		log_error("RTLIL Const width must not be negative");
+
+	if (width > 0x1000000)
+		log_error("RTLIL Const width must be less than 2^24");
+
 	flags = RTLIL::CONST_FLAG_NONE;
 	new ((void*)&bits_) bitvectype();
 	tag = backing_tag::bits;
@@ -247,6 +262,10 @@ RTLIL::Const::Const(RTLIL::State bit, int width)
 
 RTLIL::Const::Const(const std::vector<bool> &bits)
 {
+
+	if (bits.size() > 0x1000000)
+		log_error("RTLIL Const width must be less than 2^24");
+
 	flags = RTLIL::CONST_FLAG_NONE;
 	new ((void*)&bits_) bitvectype();
 	tag = backing_tag::bits;
@@ -446,6 +465,10 @@ std::string RTLIL::Const::as_string(const char* any) const
 
 RTLIL::Const RTLIL::Const::from_string(const std::string &str)
 {
+
+	if (str.size() > 0x1000000)
+		log_error("RTLIL width must be less than 2^24");
+
 	Const c;
 	bitvectype& bv = c.get_bits();
 	bv.reserve(str.size());

tests/verific/blackbox.ys

@@ -0,0 +1,24 @@
+verific -sv -lib <<EOF
+module TEST_CELL(input clk, input a, input b, output reg c);
+parameter PATH = "DEFAULT";
+always @(posedge clk) begin
+    if (PATH=="DEFAULT")
+		c <= a;
+	else 
+		c <= b;
+end
+
+endmodule
+EOF
+
+verific -sv <<EOF
+module top(input clk, input a, input b, output c, output d);
+	TEST_CELL  #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
+	TEST_CELL  #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
+endmodule
+EOF
+
+verific -import top
+hierarchy -top top
+stat
+select -assert-count 2 t:TEST_CELL