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7 Commits
a77e5ddc4c ... d736c66dc3

Author SHA1 Message Date
Zapta d736c66dc3
Merge 36c244aeda into 29e8812bab 2024-11-26 04:07:21 +13:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Miodrag Milanović 9512ec4bbc
Merge pull request #4764 from YosysHQ/micko/verific_vhdl_assert 
verific : VHDL assert DFF initial value set on Verific library patch
 2024-11-25 15:06:36 +01:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Zapta 36c244aeda Merge remote-tracking branch 'upstream' 2024-03-04 14:55:14 -08:00
Zapta 672c89498a Added to the Show command a -wireshape <graphviz-shape> flag. 
This allows to control the shape of wire nodes, for example, -wireshape plaintext.
The motivation is to allow the user to reduce visual loads of wires.
This does not change the default behavior of using a diamond shape.
 2024-03-02 11:20:53 -08:00
3 changed files with 44 additions and 13 deletions
Show Stats Expand all files Collapse all files

7
frontends/verific/verific.cc
View File

@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log(" assert condition %s.\n", log_signal(cond));
Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
// Initialize FF feeding condition to 1, in case it is not
// used by rest of design logic, to prevent failing on
// initial uninitialized state
if (cond.is_wire() && !cond.wire->name.isPublic())
cond.wire->attributes[ID::init] = Const(1,1);
import_attributes(cell->attributes, inst);
continue;
}
@ -3428,6 +3422,7 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1);
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
RuntimeFlags::SetVar("veri_create_empty_box", 1);
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

26
passes/cmds/show.cc
View File

@ -60,6 +60,7 @@ struct ShowWorker
RTLIL::Module *module;
uint32_t currentColor;
bool genWidthLabels;
std::string wireshape;
bool genSignedLabels;
bool stretchIO;
bool enumerateIds;
@ -429,16 +430,19 @@ struct ShowWorker
std::map<std::string, std::string> wires_on_demand;
for (auto wire : module->selected_wires()) {
const char *shape = "diamond";
std::string shape = wireshape;
if (wire->port_input || wire->port_output)
shape = "octagon";
const bool is_borderless = (shape == "plaintext") || (shape == "plain") || (shape == "none");
if (wire->name.isPublic()) {
std::string src_href;
if (href && wire->attributes.count(ID::src) > 0)
src_href = stringf(", href=\"%s\" ", escape(wire->attributes.at(ID::src).decode_string()));
fprintf(f, "n%d [ shape=%s, label=\"%s\", %s%s];\n",
id2num(wire->name), shape, findLabel(wire->name.str()),
nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(),
fprintf(f, "n%d [ shape=%s,%s label=\"%s\", %s%s];\n",
id2num(wire->name), shape.c_str(), is_borderless? " margin=0, width=0" : "", findLabel(wire->name.str()),
is_borderless
? "color=\"none\", fontcolor=\"black\""
: nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str(),
src_href.c_str());
if (wire->port_input)
all_sources.insert(stringf("n%d", id2num(wire->name)));
@ -617,10 +621,10 @@ struct ShowWorker
}
ShowWorker(FILE *f, RTLIL::Design *design, std::vector<RTLIL::Design*> &libs, uint32_t colorSeed, bool genWidthLabels,
bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href,
const std::string wireshape, bool genSignedLabels, bool stretchIO, bool enumerateIds, bool abbreviateIds, bool notitle, bool href,
const std::vector<std::pair<std::string, RTLIL::Selection>> &color_selections,
const std::vector<std::pair<std::string, RTLIL::Selection>> &label_selections, RTLIL::IdString colorattr) :
f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels),
f(f), design(design), currentColor(colorSeed), genWidthLabels(genWidthLabels), wireshape(wireshape),
genSignedLabels(genSignedLabels), stretchIO(stretchIO), enumerateIds(enumerateIds), abbreviateIds(abbreviateIds),
notitle(notitle), href(href), color_selections(color_selections), label_selections(label_selections), colorattr(colorattr)
{
@ -708,6 +712,9 @@ struct ShowPass : public Pass {
log(" Use the specified attribute to assign colors. A unique color is\n");
log(" assigned to each unique value of this attribute.\n");
log("\n");
log(" -wireshape <graphviz_shape>\n");
log(" Use the specified shape for wire nodes. E.g. plaintext.\n");
log("\n");
log(" -width\n");
log(" annotate buses with a label indicating the width of the bus.\n");
log("\n");
@ -766,6 +773,7 @@ struct ShowPass : public Pass {
std::string prefix = stringf("%s/.yosys_show", getenv("HOME") ? getenv("HOME") : ".");
#endif
std::string viewer_exe;
std::string flag_wireshape = "diamond";
std::vector<std::string> libfiles;
std::vector<RTLIL::Design*> libs;
uint32_t colorSeed = 0;
@ -830,6 +838,10 @@ struct ShowPass : public Pass {
format = args[++argidx];
continue;
}
if (arg == "-wireshape" && argidx+1 < args.size()) {
flag_wireshape = args[++argidx];
continue;
}
if (arg == "-width") {
flag_width= true;
continue;
@ -912,7 +924,7 @@ struct ShowPass : public Pass {
delete lib;
log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str());
}
ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr);
ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_wireshape, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr);
fclose(f);
for (auto lib : libs)

24
tests/verific/blackbox.ys Normal file
View File

@ -0,0 +1,24 @@
verific -sv -lib <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
always @(posedge clk) begin
if (PATH=="DEFAULT")
c <= a;
else
c <= b;
end
endmodule
EOF
verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF
verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL