Merge 9142bb263b into 56b80bdd22

peepopt shiftadd: Only match for sufficiently small constant widths

libs/ezsat/demo_cmp.cc

@@ -19,6 +19,7 @@
 
 #include "ezminisat.h"
 #include <assert.h>
+#include <stdlib.h>
 
 #define INIT_X 123456789
 #define INIT_Y 362436069
@@ -143,4 +144,3 @@ int main()
 	}
 	return 0;
 }
-

libs/ezsat/demo_vec.cc

@@ -19,6 +19,7 @@
 
 #include "ezminisat.h"
 #include <assert.h>
+#include <stdlib.h>
 
 #define INIT_X 123456789
 #define INIT_Y 362436069
@@ -109,4 +110,3 @@ int main()
 
 	return 0;
 }
-

misc/py_wrap_generator.py

@@ -1273,6 +1273,11 @@ class WFunction:
 		func.duplicate = False
 		func.namespace = namespace
 		str_def = str_def.replace("operator ","operator")
+
+		# remove attributes from the start
+		if str.startswith(str_def, "[[") and "]]" in str_def:
+			str_def = str_def[str_def.find("]]")+2:]
+
 		if str.startswith(str_def, "static "):
 			func.is_static = True
 			str_def = str_def[7:]

passes/opt/opt_demorgan.cc

@@ -39,6 +39,10 @@ void demorgan_worker(
 		return;
 
 	auto insig = sigmap(cell->getPort(ID::A));
+
+	if (GetSize(insig) < 1)
+		return;
+
 	log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
 	int num_inverted = 0;
 	for(int i=0; i<GetSize(insig); i++)

passes/opt/opt_reduce.cc

@@ -89,6 +89,9 @@ struct OptReduceWorker
 		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 		new_sig_a.sort_and_unify();
 
+		if (GetSize(new_sig_a) == 0)
+			new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
+
 		if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
 			did_something = true;

passes/pmgen/peepopt_shiftadd.pmg

@@ -53,6 +53,11 @@ match add
 	select port(add, constport).is_fully_const()
 	define <IdString> varport (constport == \A ? \B : \A)
 
+	// only optimize for constants up to a fixed width. this prevents cases
+	// with a blowup in internal term size and prevents larger constants being
+	// casted to int incorrectly
+	select (GetSize(port(add, constport)) <= 24)
+
 	// if a value of var is able to wrap the output, the transformation might give wrong results
 	// an addition/substraction can at most flip one more bit than the largest operand (the carry bit)
 	// as long as the output can show this bit, no wrap should occur (assuming all signed-ness make sense)

passes/proc/proc_dff.cc

@@ -262,7 +262,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 		{
 			log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
 			gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
-			return;
+			continue;
 		}
 
 		// If there is a reset condition in the async rules, use it
@@ -277,7 +277,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 					sync_edge->type == RTLIL::SyncType::STp,
 					sync_level && sync_level->type == RTLIL::SyncType::ST1,
 					sync_edge->signal, sync_level->signal, proc);
-			return;
+			continue;
 		}
 
 		gen_dff(mod, insig, rstval.as_const(), sig_q,

techlibs/gowin/cells_xtra.py

@@ -65,6 +65,8 @@ if __name__ == '__main__':
 
     dirs = [
         os.path.join(args.gowin_dir, 'IDE/simlib/gw1n/'),
+        os.path.join(args.gowin_dir, 'IDE/simlib/gw2a/'),
+        os.path.join(args.gowin_dir, 'IDE/simlib/gw5a/'),
     ]
 
     with open('cells_xtra.v', 'w') as fout:

tests/opt/bug4610.ys

@@ -0,0 +1,15 @@
+read_ilang <<EOT
+autoidx 1
+module \top
+  wire output 1 \Y
+  cell $reduce_or $reduce_or$rtl.v:29$20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 0
+    parameter \Y_WIDTH 1
+    connect \A { }
+    connect \Y \Y
+  end
+end
+EOT
+
+equiv_opt -assert opt_demorgan

tests/opt/opt_reduce_andor.ys

@@ -0,0 +1,14 @@
+# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
+
+read_verilog <<EOT
+module reduce_const(output wire o, output wire a);
+    wire [3:0] zero = 4'b0000;
+    wire [3:0] ones = 4'b1111;
+    assign o = |zero;
+    assign a = &ones;
+endmodule
+EOT
+
+equiv_opt -assert opt_reduce
+design -load postopt
+select -assert-none r:A_WIDTH=0

tests/proc/bug4712.ys

@@ -0,0 +1,31 @@
+read_rtlil <<EOT
+autoidx 1
+module \top
+  wire input 1 \clk
+  wire input 2 \rst
+
+  wire input 3 \a_r
+  wire input 4 \a_n
+  wire input 5 \b_n
+
+  wire \a
+  wire \b
+
+  process $proc
+    sync high \rst
+      update \a \a_r
+      update \b \b
+    sync posedge \clk
+      update \a \a_n
+      update \b \b_n
+  end
+end
+EOT
+
+proc_dff
+proc_clean
+
+# Processes should have been converted to one aldff and one dff
+select -assert-none p:*
+select -assert-count 1 t:$aldff
+select -assert-count 1 t:$dff