Merge e2530b30df into 5b6baa3ef1

clockgate: add -liberty

passes/cmds/Makefile.inc

@@ -15,6 +15,7 @@ OBJS += passes/cmds/scatter.o
 OBJS += passes/cmds/setundef.o
 OBJS += passes/cmds/splitnets.o
 OBJS += passes/cmds/splitcells.o
+OBJS += passes/cmds/splitfanout.o
 OBJS += passes/cmds/stat.o
 OBJS += passes/cmds/internal_stats.o
 OBJS += passes/cmds/setattr.o

passes/cmds/splitfanout.cc

@@ -0,0 +1,244 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *                2024  Akash Levy        <akash@silimate.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "kernel/utils.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SplitfanoutWorker
+{
+	Module *module;
+	SigMap sigmap;
+	dict<SigBit, tuple<IdString,IdString,int>> bit_drivers_db;
+	dict<SigBit, pool<tuple<IdString,IdString,int>>> bit_users_db;
+	TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
+
+	SplitfanoutWorker(Module *module) : module(module), sigmap(module)
+	{
+		// Add nodes to topological sorter for all selected cells
+		log("Making toposort nodes for module %s...\n", log_id(module));
+		for (auto cell : module->selected_cells())
+			toposort.node(cell->name);
+
+		// Build bit_drivers_db
+		log("Building bit_drivers_db...\n");
+		for (auto cell : module->cells()) {
+			for (auto conn : cell->connections()) {
+				if (!cell->output(conn.first)) continue;
+				for (int i = 0; i < GetSize(conn.second); i++) {
+					SigBit bit(sigmap(conn.second[i]));
+					bit_drivers_db[bit] = tuple<IdString,IdString,int>(cell->name, conn.first, i);
+				}
+			}
+		}
+
+		// Build bit_users_db and add edges to topological sorter
+		log("Building bit_users_db and adding edges to toposort...\n");
+		for (auto cell : module->cells()) {
+			for (auto conn : cell->connections()) {
+				if (!cell->input(conn.first)) continue;
+				for (int i = 0; i < GetSize(conn.second); i++) {
+					SigBit bit(sigmap(conn.second[i]));
+					if (!bit_drivers_db.count(bit)) continue;
+					bit_users_db[bit].insert(tuple<IdString,IdString,int>(cell->name,
+							conn.first, i-std::get<2>(bit_drivers_db[bit])));
+					IdString driver_cell = std::get<0>(bit_drivers_db[bit]);
+					if (toposort.has_node(driver_cell) && toposort.has_node(cell->name))
+						// toposort.edge(driver_cell, cell->name);
+						toposort.edge(cell->name, driver_cell);
+				}
+			}
+		}
+
+		// Build bit_users_db for output ports
+		log("Building bit_users_db for output ports...\n");
+		for (auto wire : module->wires()) {
+			if (!wire->port_output) continue;
+			SigSpec sig(sigmap(wire));
+			for (int i = 0; i < GetSize(sig); i++) {
+				SigBit bit(sig[i]);
+				if (!bit_drivers_db.count(bit)) continue;
+				bit_users_db[bit].insert(tuple<IdString,IdString,int>(wire->name,
+						IdString(), i-std::get<2>(bit_drivers_db[bit])));
+			}
+		}
+
+		// Sort using the topological sorter
+		log("Sorting using toposort...\n");
+		toposort.analyze_loops = false;
+		toposort.sort();
+	}
+
+	int split(Cell *cell, int limit)
+	{
+		// Get output signal/port
+		SigSpec outsig;
+		IdString outport;
+		int output_count = 0;
+		for (auto conn : cell->connections())
+			if (cell->output(conn.first)) {
+				output_count++;
+				outport = conn.first;
+				outsig = conn.second;
+			}
+		if (output_count != 1) {
+			log("Skipping %s cell %s/%s with %d output ports.\n", log_id(cell->type), log_id(module), log_id(cell), output_count);
+			return 0;
+		}
+		
+		// Check if output signal is "bit-split", skip if so
+		auto bit_users = bit_users_db[outsig[0]];
+		for (int i = 0; i < GetSize(outsig); i++) {
+			if (bit_users_db[outsig[i]] != bit_users) {
+				log("Skipping %s cell %s/%s with bit-split output.\n", log_id(cell->type), log_id(module), log_id(cell));
+				return 0;
+			}
+		}
+
+		// Skip if output signal has only one user
+		if (GetSize(bit_users) <= 1)
+			return 0;
+
+		// Skip if fanout is above limit
+		if (limit != -1 && GetSize(bit_users) > limit) {
+			log("Skipping %s cell %s/%s with high fanout %d.\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
+			return 0;
+		}
+
+		// Iterate over bit users and create a new cell for each one
+		log("Splitting %s cell %s/%s into %d copies based on fanout\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
+		int foi = 0;
+		cell->unsetPort(outport);
+		int num_new_cells = GetSize(bit_users)-1;
+		int bit_user_i = num_new_cells;
+		for (auto bit_user : bit_users)
+		{
+			// Configure the driver cell
+			IdString new_name;
+			Cell *new_cell;
+			if (bit_user_i-- != 0) { // create a new cell
+				new_name = module->uniquify(cell->name.str());
+				new_cell = module->addCell(new_name, cell);
+				// Add new cell to the bit_users_db
+				for (auto conn : new_cell->connections()) {
+					if (!new_cell->input(conn.first)) continue;
+					for (int i = 0; i < GetSize(conn.second); i++) {
+						SigBit bit(sigmap(conn.second[i]));
+						if (!bit_drivers_db.count(bit)) continue;
+						bit_users_db[bit].insert(tuple<IdString,IdString,int>(new_cell->name,
+								conn.first, i-std::get<2>(bit_drivers_db[bit])));
+					}
+				}
+			} else { // if last cell, reuse the original cell
+				new_name = cell->name;
+				new_cell = cell;
+			}
+
+			// Connect the new cell to the user
+			if (std::get<1>(bit_user) == IdString()) { // is wire
+				Wire *old_wire = module->wire(std::get<0>(bit_user));
+				Wire *new_wire = module->addWire(NEW_ID, old_wire);
+				module->swap_names(old_wire, new_wire);
+				old_wire->port_input = false;
+				old_wire->port_output = false;
+				SigSpec sig(new_wire, std::get<2>(bit_user), GetSize(outsig));
+				new_cell->setPort(outport, sig);
+			}
+			else {
+				Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig));
+				Cell *target_cell = module->cell(std::get<0>(bit_user));
+				SigSpec sig = target_cell->getPort(std::get<1>(bit_user));
+				sig.replace(std::get<2>(bit_user), new_wire);
+				module->cell(std::get<0>(bit_user))->setPort(std::get<1>(bit_user), sig);
+				new_cell->setPort(outport, new_wire);
+			}
+
+			// Log the new cell
+			log_debug("  slice %d: %s => %s\n", foi++, log_id(new_name), log_signal(new_cell->getPort(outport)));
+		}
+
+		// Fix up ports
+		module->fixup_ports();
+
+		// Return the number of new cells created
+		return num_new_cells;
+	}
+};
+
+struct SplitfanoutPass : public Pass {
+	SplitfanoutPass() : Pass("splitfanout", "split up cells with >1 fanout into copies") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    splitfanout [selection]\n");
+		log("\n");
+		log("This command copies selected cells with >1 fanout into cells with fanout 1. It\n");
+		log("is effectively the opposite of the opt_merge pass.\n");
+		log("\n");
+		log("This command operates only on cells with 1 output and no 'bit split' on that\n");
+		log("output.\n");
+		log("\n");
+		log("    -limit n\n");
+		log("        max fanout to split.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		int limit = -1;
+		log_header(design, "Executing SPLITFANOUT pass (splitting up cells with >1 fanout into copies).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// No options currently. When adding in the future make sure to update docstring with [options]
+			if (args[argidx] == "-limit" && argidx+1 < args.size()) {
+				limit = std::stoi(args[++argidx]);
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			int count_split_pre = 0;
+			int count_split_post = 0;
+
+			SplitfanoutWorker worker(module);
+			for (auto cell : worker.toposort.sorted) {
+				int n = worker.split(module->cell(cell), limit);
+				count_split_pre += (n != 0);
+				count_split_post += n;
+			}
+
+			if (count_split_pre)
+				log("Split %d cells in module '%s' into %d copies based on fanout.\n",
+					count_split_pre, log_id(module), count_split_post);
+		}
+
+		Pass::call(design, "clean *");
+	}
+} SplitfanoutPass;
+
+PRIVATE_NAMESPACE_END

passes/techmap/clockgate.cc

@@ -1,5 +1,6 @@
 #include "kernel/yosys.h"
 #include "kernel/ff.h"
+#include "libparse.h"
 #include <optional>
 
 USING_YOSYS_NAMESPACE
@@ -10,6 +11,7 @@ struct ClockGateCell {
 	IdString ce_pin;
 	IdString clk_in_pin;
 	IdString clk_out_pin;
+	std::vector<IdString> tie_lo_pins;
 };
 
 ClockGateCell icg_from_arg(std::string& name, std::string& str) {
@@ -37,6 +39,166 @@ ClockGateCell icg_from_arg(std::string& name, std::string& str) {
 	return c;
 }
 
+static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
+	find_icgs(std::string filename, std::vector<std::string> const& dont_use_cells) {
+	std::ifstream f;
+	f.open(filename.c_str());
+	if (f.fail())
+		log_cmd_error("Can't open liberty file `%s': %s\n", filename.c_str(), strerror(errno));
+	LibertyParser libparser(f);
+	f.close();
+	auto ast = libparser.ast;
+
+	// We will pick the most suitable ICG absed on tie_lo count and area
+	struct ICGRankable : public ClockGateCell { double area; };
+	std::optional<ICGRankable> best_pos;
+	std::optional<ICGRankable> best_neg;
+
+	if (ast->id != "library")
+		log_error("Format error in liberty file.\n");
+
+	// This is a lot of boilerplate, isn't it?
+	for (auto cell : ast->children)
+	{
+		if (cell->id != "cell" || cell->args.size() != 1)
+			continue;
+
+		const LibertyAst *dn = cell->find("dont_use");
+		if (dn != nullptr && dn->value == "true")
+			continue;
+
+		bool dont_use = false;
+		for (auto dont_use_cell : dont_use_cells)
+		{
+			if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
+			{
+				dont_use = true;
+				break;
+			}
+		}
+		if (dont_use)
+			continue;
+
+		const LibertyAst *icg_kind_ast = cell->find("clock_gating_integrated_cell");
+		if (icg_kind_ast == nullptr)
+			continue;
+
+		auto cell_name = cell->args[0];
+		auto icg_kind = icg_kind_ast->value;
+		auto starts_with = [&](std::string prefix) {
+			return icg_kind.compare(0, prefix.size(), prefix) == 0;
+		};
+		bool clk_pol;
+		if (icg_kind == "latch_posedge" || starts_with("latch_posedge_")) {
+			clk_pol = true;
+		} else if (icg_kind == "latch_negedge" || starts_with("latch_negedge_")) {
+			clk_pol = false;
+		} else {
+			log("Ignoring ICG primitive %s of kind '%s'\n", cell_name.c_str(), icg_kind.c_str());
+			continue;
+		}
+
+		log_debug("maybe valid icg: %s\n", cell_name.c_str());
+		ClockGateCell icg_interface;
+		icg_interface.name = RTLIL::escape_id(cell_name);
+
+		for (auto pin : cell->children) {
+			if (pin->id != "pin" || pin->args.size() != 1)
+				continue;
+
+			if (auto clk = pin->find("clock_gate_clock_pin")) {
+				if (!icg_interface.clk_in_pin.empty()) {
+					log_warning("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n",
+						cell_name.c_str());
+					continue;
+				} else
+					icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]);
+			} else if (auto gclk = pin->find("clock_gate_out_pin")) {
+				if (!icg_interface.clk_out_pin.empty()) {
+					log_warning("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n",
+						cell_name.c_str());
+					continue;
+				} else
+					icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]);
+			} else if (auto en = pin->find("clock_gate_enable_pin")) {
+				if (!icg_interface.ce_pin.empty()) {
+					log_warning("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n",
+						cell_name.c_str());
+					continue;
+				} else
+					icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]);
+			} else if (auto se = pin->find("clock_gate_test_pin")) {
+				icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0]));
+			} else {
+				const LibertyAst *dir = pin->find("direction");
+				if (dir->value == "internal")
+					continue;
+
+				log_warning("Malformed liberty file - extra pin %s in cell %s\n",
+					pin->args[0].c_str(), cell_name.c_str());
+				continue;
+			}
+		}
+
+		if (icg_interface.clk_in_pin.empty()) {
+			log_warning("Malformed liberty file - missing clock_gate_clock_pin in cell %s",
+				cell_name.c_str());
+			continue;
+		}
+		if (icg_interface.clk_out_pin.empty()) {
+			log_warning("Malformed liberty file - missing clock_gate_out_pin in cell %s",
+				cell_name.c_str());
+			continue;
+		}
+		if (icg_interface.ce_pin.empty()) {
+			log_warning("Malformed liberty file - missing clock_gate_enable_pin in cell %s",
+				cell_name.c_str());
+			continue;
+		}
+
+		double area = 0;
+		const LibertyAst *ar = cell->find("area");
+		if (ar != nullptr && !ar->value.empty())
+			area = atof(ar->value.c_str());
+
+		std::optional<ICGRankable>& icg_to_beat = clk_pol ? best_pos : best_neg;
+
+		bool winning = false;
+		if (icg_to_beat) {
+			log_debug("ties: %zu ? %zu\n", icg_to_beat->tie_lo_pins.size(),
+				icg_interface.tie_lo_pins.size());
+			log_debug("area: %f ? %f\n", icg_to_beat->area, area);
+
+			// Prefer fewer test enables over area reduction (unlikely to matter)
+			auto goal = std::make_pair(icg_to_beat->tie_lo_pins.size(), icg_to_beat->area);
+			auto cost = std::make_pair(icg_interface.tie_lo_pins.size(), area);
+			winning = cost < goal;
+
+			if (winning)
+				log_debug("%s beats %s\n", icg_interface.name.c_str(), icg_to_beat->name.c_str());
+		} else {
+			log_debug("%s is the first of its polarity\n", icg_interface.name.c_str());
+			winning = true;
+		}
+		if (winning) {
+			ICGRankable new_icg {icg_interface, area};
+			icg_to_beat.emplace(new_icg);
+		}
+	}
+
+	std::optional<ClockGateCell> pos;
+	std::optional<ClockGateCell> neg;
+	if (best_pos) {
+		log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str());
+		pos.emplace(*best_pos);
+	}
+	if (best_neg) {
+		log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str());
+		neg.emplace(*best_neg);
+	}
+	return std::make_pair(pos, neg);
+}
+
 struct ClockgatePass : public Pass {
 	ClockgatePass() : Pass("clockgate", "extract clock gating out of flip flops") { }
 	void help() override {
@@ -60,12 +222,20 @@ struct ClockgatePass : public Pass {
 		log("        user-specified <celltype> ICG (integrated clock gating)\n");
 		log("        cell with ports named <ce>, <clk>, <gclk>.\n");
 		log("        The ICG's clock enable pin must be active high.\n");
+		log("    -liberty <filename>\n");
+		log("        If specified, ICGs will be selected from the liberty file\n");
+		log("        if available. Priority is given to cells with fewer tie_lo\n");
+		log("        inputs and smaller size. This removes the need to manually\n");
+		log("        specify -pos or -neg and -tie_lo.\n");
+		log("    -dont_use <celltype>\n");
+		log("        Cells <celltype> won't be considered when searching for ICGs\n");
+		log("        in the liberty file specified by -liberty.\n");
 		log("    -tie_lo <port_name>\n");
 		log("        Port <port_name> of the ICG will be tied to zero.\n");
 		log("        Intended for DFT scan-enable pins.\n");
 		log("    -min_net_size <n>\n");
 		log("        Only transform sets of at least <n> eligible FFs.\n");
-		// log("        \n");
+		log("        \n");
 	}
 
 	// One ICG will be generated per ClkNetInfo
@@ -110,7 +280,9 @@ struct ClockgatePass : public Pass {
 
 		std::optional<ClockGateCell> pos_icg_desc;
 		std::optional<ClockGateCell> neg_icg_desc;
-		std::vector<std::string> tie_lo_ports;
+		std::vector<std::string> tie_lo_pins;
+		std::string liberty_file;
+		std::vector<std::string> dont_use_cells;
 		int min_net_size = 0;
 
 		size_t argidx;
@@ -126,13 +298,33 @@ struct ClockgatePass : public Pass {
 				neg_icg_desc = icg_from_arg(name, rest);
 			}
 			if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) {
-				tie_lo_ports.push_back(RTLIL::escape_id(args[++argidx]));
+				tie_lo_pins.push_back(RTLIL::escape_id(args[++argidx]));
+			}
+			if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
+				liberty_file = args[++argidx];
+				rewrite_filename(liberty_file);
+			}
+			if (args[argidx] == "-dont_use" && argidx+1 < args.size()) {
+				dont_use_cells.push_back(args[++argidx]);
+				continue;
 			}
 			if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
 				min_net_size = atoi(args[++argidx].c_str());
 			}
 		}
 
+		if (!liberty_file.empty())
+			std::tie(pos_icg_desc, neg_icg_desc) =
+				find_icgs(liberty_file, dont_use_cells);
+		else {
+			for (auto pin : tie_lo_pins) {
+				if (pos_icg_desc)
+					pos_icg_desc->tie_lo_pins.push_back(pin);
+				if (neg_icg_desc)
+					neg_icg_desc->tie_lo_pins.push_back(pin);
+			}
+		}
+
 		extra_args(args, argidx, design);
 
 		pool<Cell*> ce_ffs;
@@ -185,7 +377,7 @@ struct ClockgatePass : public Pass {
 				gclk.new_net = module->addWire(NEW_ID);
 				icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
 				// Tie low DFT ports like scan chain enable
-				for (auto port : tie_lo_ports)
+				for (auto port : matching_icg_desc->tie_lo_pins)
 					icg->setPort(port, Const(0, 1));
 				// Fix CE polarity if needed
 				if (!clk.pol_ce) {

tests/opt/bug4610.ys

@@ -1,4 +1,4 @@
-read_ilang <<EOT
+read_rtlil <<EOT
 autoidx 1
 module \top
   wire output 1 \Y

tests/techmap/clockgate.lib

@@ -0,0 +1,107 @@
+library(test) {
+    /* Integrated clock gating cells */
+    cell (pos_small_tielo) {
+        area : 1;
+        clock_gating_integrated_cell : latch_posedge_precontrol;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+        pin (SE) {
+            clock_gate_test_pin : true;
+            direction : input;
+        }
+    }
+    cell (pos_big) {
+        area : 10;
+        clock_gating_integrated_cell : latch_posedge;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+    }
+    cell (pos_small) {
+        area : 1;
+        clock_gating_integrated_cell : latch_posedge;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+    }
+    cell (neg_big) {
+        area : 10;
+        clock_gating_integrated_cell : latch_negedge;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+    }
+    cell (neg_small_tielo) {
+        area : 1;
+        clock_gating_integrated_cell : latch_negedge_precontrol;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+        pin (SE) {
+            clock_gate_test_pin : true;
+            direction : input;
+        }
+    }
+    cell (neg_small) {
+        area : 1;
+        clock_gating_integrated_cell : latch_negedge;
+        pin (GCLK) {
+            clock_gate_out_pin : true;
+            direction : output;
+        }
+        pin (CLK) {
+            clock_gate_clock_pin : true;
+            direction : input;
+        }
+        pin (CE) {
+            clock_gate_enable_pin : true;
+            direction : input;
+        }
+    }
+}

tests/techmap/clockgate.ys

@@ -61,7 +61,7 @@ clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
 # falling edge clock flops don't get matched on -pos
 select -module dffe_00 -assert-count 0 t:\\pdk_icg
 select -module dffe_01 -assert-count 0 t:\\pdk_icg
-# falling edge clock flops do get matched on -pos
+# rising edge clock flops do get matched on -pos
 select -module dffe_10 -assert-count 1 t:\\pdk_icg
 select -module dffe_11 -assert-count 1 t:\\pdk_icg
 # if necessary, EN is inverted, since the given ICG
@@ -79,10 +79,10 @@ select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
 design -load before
 clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
 
-# rising edge clock flops don't get matched on -neg
+# falling edge clock flops do get matched on -neg
 select -module dffe_00 -assert-count 1 t:\\pdk_icg
 select -module dffe_01 -assert-count 1 t:\\pdk_icg
-# rising edge clock flops do get matched on -neg
+# rising edge clock flops don't get matched on -neg
 select -module dffe_10 -assert-count 0 t:\\pdk_icg
 select -module dffe_11 -assert-count 0 t:\\pdk_icg
 # if necessary, EN is inverted, since the given ICG
@@ -193,4 +193,55 @@ select -assert-count 1 t:\\pdk_icg
 
 #------------------------------------------------------------------------------
 
-# TODO test -tie_lo
+design -load before
+clockgate -liberty clockgate.lib
+
+# rising edge ICGs
+select -module dffe_00 -assert-count 0 t:\\pos_small
+select -module dffe_01 -assert-count 0 t:\\pos_small
+
+select -module dffe_10 -assert-count 1 t:\\pos_small
+select -module dffe_11 -assert-count 1 t:\\pos_small
+
+# falling edge ICGs
+select -module dffe_00 -assert-count 1 t:\\neg_small
+select -module dffe_01 -assert-count 1 t:\\neg_small
+
+select -module dffe_10 -assert-count 0 t:\\neg_small
+select -module dffe_11 -assert-count 0 t:\\neg_small
+
+# and nothing else
+select -module dffe_00 -assert-count 0 t:\\pos_big
+select -module dffe_01 -assert-count 0 t:\\pos_big
+select -module dffe_10 -assert-count 0 t:\\pos_big
+select -module dffe_11 -assert-count 0 t:\\pos_big
+select -module dffe_00 -assert-count 0 t:\\pos_small_tielo
+select -module dffe_01 -assert-count 0 t:\\pos_small_tielo
+select -module dffe_10 -assert-count 0 t:\\pos_small_tielo
+select -module dffe_11 -assert-count 0 t:\\pos_small_tielo
+select -module dffe_00 -assert-count 0 t:\\neg_big
+select -module dffe_01 -assert-count 0 t:\\neg_big
+select -module dffe_10 -assert-count 0 t:\\neg_big
+select -module dffe_11 -assert-count 0 t:\\neg_big
+select -module dffe_00 -assert-count 0 t:\\neg_small_tielo
+select -module dffe_01 -assert-count 0 t:\\neg_small_tielo
+select -module dffe_10 -assert-count 0 t:\\neg_small_tielo
+select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
+
+# if necessary, EN is inverted, since the given ICG
+# is assumed to have an active-high EN
+select -module dffe_10 -assert-count 1 t:\$_NOT_
+select -module dffe_11 -assert-count 0 t:\$_NOT_
+
+#------------------------------------------------------------------------------
+
+design -load before
+clockgate -liberty clockgate.lib -dont_use pos_small -dont_use neg_small
+
+# rising edge ICGs
+select -module dffe_10 -assert-count 1 t:\\pos_big
+select -module dffe_11 -assert-count 1 t:\\pos_big
+
+# falling edge ICGs
+select -module dffe_00 -assert-count 1 t:\\neg_big
+select -module dffe_01 -assert-count 1 t:\\neg_big