.mailmap

@@ -1,3 +0,0 @@
-Marcelina Kościelnicka <mwk@0x04.net>
-Marcelina Kościelnicka <mwk@0x04.net> <koriakin@0x04.net>
-Marcelina Kościelnicka <mwk@0x04.net> <marcin@symbioticeda.com>

.travis.yml

@@ -0,0 +1,144 @@
+sudo: false
+language: cpp
+
+cache:
+ ccache: true
+ directories:
+  - ~/.local-bin
+
+
+env:
+  global:
+    - MAKEFLAGS="-j 2"
+
+matrix:
+  include:
+    # Latest gcc-4.8, earliest version supported by Travis
+    - os: linux
+      addons:
+        apt:
+          packages:
+            - g++-4.8
+            - gperf
+            - build-essential
+            - bison
+            - flex
+            - libreadline-dev
+            - gawk
+            - tcl-dev
+            - libffi-dev
+            - git
+            - graphviz
+            - xdot
+            - pkg-config
+            - python
+            - python3
+            - libboost-system-dev
+            - libboost-python-dev
+            - libboost-filesystem-dev
+            - zlib1g-dev
+      env:
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8"
+
+    # Latest gcc supported on Travis Linux
+    - os: linux
+      addons:
+        apt:
+          sources:
+            - ubuntu-toolchain-r-test
+          packages:
+            - g++-9
+            - gperf
+            - build-essential
+            - bison
+            - flex
+            - libreadline-dev
+            - gawk
+            - tcl-dev
+            - libffi-dev
+            - git
+            - graphviz
+            - xdot
+            - pkg-config
+            - python
+            - python3
+            - libboost-system-dev
+            - libboost-python-dev
+            - libboost-filesystem-dev
+            - zlib1g-dev
+      env:
+        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-9 && CXX=g++-9"
+
+    # Clang which ships on Trusty Linux
+    - os: linux
+      addons:
+        apt:
+          sources:
+            - ubuntu-toolchain-r-test
+            - llvm-toolchain-precise-3.8
+          packages:
+            - clang-3.8
+            - gperf
+            - build-essential
+            - bison
+            - flex
+            - libreadline-dev
+            - gawk
+            - tcl-dev
+            - libffi-dev
+            - git
+            - graphviz
+            - xdot
+            - pkg-config
+            - python
+            - python3
+            - libboost-system-dev
+            - libboost-python-dev
+            - libboost-filesystem-dev
+            - zlib1g-dev
+      env:
+        - MATRIX_EVAL="CONFIG=clang && CC=clang-3.8 && CXX=clang++-3.8"
+
+    # Latest clang supported by Travis Linux
+    - os: linux
+      addons:
+        apt:
+          sources:
+            - llvm-toolchain-xenial-8
+          packages:
+            - clang-8
+            - gperf
+            - build-essential
+            - bison
+            - flex
+            - libreadline-dev
+            - gawk
+            - tcl-dev
+            - libffi-dev
+            - git
+            - graphviz
+            - xdot
+            - pkg-config
+            - python
+            - python3
+            - libboost-system-dev
+            - libboost-python-dev
+            - libboost-filesystem-dev
+            - zlib1g-dev
+      env:
+        - MATRIX_EVAL="CONFIG=clang && CC=clang-8 && CXX=clang++-8"
+
+#   # Latest clang on Mac OS X
+#   - os: osx
+#     osx_image: xcode9.4
+#     env:
+#       - MATRIX_EVAL="CONFIG=clang && CC=clang && CXX=clang++"
+
+before_install:
+  - ./.travis/setup.sh
+
+script:
+  - ./.travis/build-and-test.sh
+
+after_success:
+  - ./.travis/deploy-after-success.sh

.travis/build-and-test.sh

@@ -0,0 +1,51 @@
+#! /bin/bash
+
+set -e
+
+source .travis/common.sh
+
+##########################################################################
+
+echo
+echo 'Configuring...' && echo -en 'travis_fold:start:script.configure\\r'
+echo
+
+if [ "$CONFIG" = "gcc" ]; then
+	echo "Configuring for gcc."
+	make config-gcc
+elif [ "$CONFIG" = "clang" ]; then
+	echo "Configuring for clang."
+	make config-clang
+fi
+
+echo
+echo -en 'travis_fold:end:script.configure\\r'
+echo
+
+##########################################################################
+
+echo
+echo 'Building...' && echo -en 'travis_fold:start:script.build\\r'
+echo
+
+make CC=$CC CXX=$CC LD=$CC
+
+echo
+echo -en 'travis_fold:end:script.build\\r'
+echo
+
+##########################################################################
+
+./yosys tests/simple/fiedler-cooley.v
+
+echo
+echo 'Testing...' && echo -en 'travis_fold:start:script.test\\r'
+echo
+
+make test
+
+echo
+echo -en 'travis_fold:end:script.test\\r'
+echo
+
+##########################################################################

.travis/common.sh

@@ -0,0 +1,15 @@
+#! /bin/bash
+
+# Setup the CC / CXX from the matrix config
+eval "${MATRIX_EVAL}"
+
+# Look for location binaries first
+export PATH="$HOME/.local-bin/bin:$PATH"
+
+# OS X specific common setup
+if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
+	export PATH="/usr/local/opt/ccache/libexec:$PATH"
+fi
+
+# Parallel builds!
+MAKEFLAGS="-j 2"

.travis/deploy-after-success.sh

@@ -0,0 +1,6 @@
+#! /bin/bash
+
+set -x
+set -e
+
+# FIXME: Upload the build results somewhere...

.travis/setup.sh

@@ -0,0 +1,63 @@
+#! /bin/bash
+
+set -e
+
+source .travis/common.sh
+
+##########################################################################
+
+# Output status information.
+(
+	set +e
+	set -x
+	git status
+	git branch -v
+	git log -n 5 --graph
+	git log --format=oneline -n 20 --graph
+)
+echo
+echo -en 'travis_fold:end:before_install.git\\r'
+echo
+
+##########################################################################
+
+# Mac OS X specific setup.
+if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
+	(
+		echo
+		echo 'Setting up brew...' && echo -en 'travis_fold:start:before_install.brew\\r'
+		echo
+		brew update
+		brew tap Homebrew/bundle
+		brew bundle
+		brew install ccache
+		echo
+		echo -en 'travis_fold:end:before_install.brew\\r'
+		echo
+	)
+fi
+
+##########################################################################
+
+# Install iverilog
+(
+	if [ ! -e ~/.local-bin/bin/iverilog ]; then
+		echo
+		echo 'Building iverilog...' && echo -en 'travis_fold:start:before_install.iverilog\\r'
+		echo
+		mkdir -p ~/.local-src
+		mkdir -p ~/.local-bin
+		cd ~/.local-src
+		git clone git://github.com/steveicarus/iverilog.git
+		cd iverilog
+		autoconf
+		CC=gcc CXX=g++ ./configure --prefix=$HOME/.local-bin
+		make
+		make install
+		echo
+		echo -en 'travis_fold:end:before_install.iverilog\\r'
+		echo
+	fi
+)
+
+##########################################################################

kernel/hashlib.h

@@ -66,12 +66,6 @@ struct hash_int_ops {
 	}
 };
 
-template<> struct hash_ops<bool> : hash_int_ops
-{
-	static inline unsigned int hash(bool a) {
-		return a ? 1 : 0;
-	}
-};
 template<> struct hash_ops<int32_t> : hash_int_ops
 {
 	static inline unsigned int hash(int32_t a) {

passes/opt/opt_mem_feedback.cc

@@ -18,25 +18,22 @@
  */
 
 #include "kernel/yosys.h"
+#include "kernel/satgen.h"
 #include "kernel/sigtools.h"
-#include "kernel/mem.h"
+#include "kernel/modtools.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-// Describes found feedback path.
-struct FeedbackPath {
-	// Which write port it is.
-	int wrport_idx;
-	// Which data bit of that write port it is.
-	int data_bit_idx;
-	// Values of all mux select signals that need to be set to select this path.
-	dict<RTLIL::SigBit, bool> condition;
-	// The exact feedback bit used (used to match read port).
-	SigBit feedback_bit;
+bool memrd_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
+{
+	return a->name < b->name;
+}
 
-	FeedbackPath(int wrport_idx, int data_bit_idx, dict<RTLIL::SigBit, bool> condition, SigBit feedback_bit) : wrport_idx(wrport_idx), data_bit_idx(data_bit_idx), condition(condition), feedback_bit(feedback_bit) {}
-};
+bool memwr_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
+{
+	return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
+}
 
 struct OptMemFeedbackWorker
 {
@@ -44,32 +41,24 @@ struct OptMemFeedbackWorker
 	RTLIL::Module *module;
 	SigMap sigmap, sigmap_xmux;
 
-	dict<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux;
-	dict<RTLIL::SigBit, int> sig_users_count;
-	dict<pair<pool<dict<SigBit, bool>>, SigBit>, SigBit> conditions_logic_cache;
+	std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, int>> sig_to_mux;
+	std::map<pair<std::set<std::map<SigBit, bool>>, SigBit>, SigBit> conditions_logic_cache;
 
 
 	// -----------------------------------------------------------------
 	// Converting feedbacks to async read ports to proper enable signals
 	// -----------------------------------------------------------------
 
-	void find_data_feedback(const pool<RTLIL::SigBit> &async_rd_bits, RTLIL::SigBit sig,
-			const dict<RTLIL::SigBit, bool> &state,
-			int wrport_idx, int data_bit_idx,
-			std::vector<FeedbackPath> &paths)
+	bool find_data_feedback(const std::set<RTLIL::SigBit> &async_rd_bits, RTLIL::SigBit sig,
+			std::map<RTLIL::SigBit, bool> &state, std::set<std::map<RTLIL::SigBit, bool>> &conditions)
 	{
 		if (async_rd_bits.count(sig)) {
-			paths.push_back(FeedbackPath(wrport_idx, data_bit_idx, state, sig));
-			return;
-		}
-
-		if (sig_users_count[sig] != 1) {
-			// Only descend into muxes if we're the only user.
-			return;
+			conditions.insert(state);
+			return true;
 		}
 
 		if (sig_to_mux.count(sig) == 0)
-			return;
+			return false;
 
 		RTLIL::Cell *cell = sig_to_mux.at(sig).first;
 		int bit_idx = sig_to_mux.at(sig).second;
@@ -80,32 +69,46 @@ struct OptMemFeedbackWorker
 		std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
 		log_assert(sig_y.at(bit_idx) == sig);
 
-		for (int i = 0; i < GetSize(sig_s); i++)
+		for (int i = 0; i < int(sig_s.size()); i++)
 			if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
-				find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, wrport_idx, data_bit_idx, paths);
-				return;
+				if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) {
+					RTLIL::SigSpec new_b = cell->getPort(ID::B);
+					new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+					cell->setPort(ID::B, new_b);
+				}
+				return false;
 			}
 
 
-		for (int i = 0; i < GetSize(sig_s); i++)
+		for (int i = 0; i < int(sig_s.size()); i++)
 		{
 			if (state.count(sig_s[i]) && state.at(sig_s[i]) == false)
 				continue;
 
-			dict<RTLIL::SigBit, bool> new_state = state;
+			std::map<RTLIL::SigBit, bool> new_state = state;
 			new_state[sig_s[i]] = true;
 
-			find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, wrport_idx, data_bit_idx, paths);
+			if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) {
+				RTLIL::SigSpec new_b = cell->getPort(ID::B);
+				new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+				cell->setPort(ID::B, new_b);
+			}
 		}
 
-		dict<RTLIL::SigBit, bool> new_state = state;
-		for (auto bit : sig_s)
-			new_state[bit] = false;
+		std::map<RTLIL::SigBit, bool> new_state = state;
+		for (int i = 0; i < int(sig_s.size()); i++)
+			new_state[sig_s[i]] = false;
 
-		find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, wrport_idx, data_bit_idx, paths);
+		if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) {
+			RTLIL::SigSpec new_a = cell->getPort(ID::A);
+			new_a.replace(bit_idx, RTLIL::State::Sx);
+			cell->setPort(ID::A, new_a);
+		}
+
+		return false;
 	}
 
-	RTLIL::SigBit conditions_to_logic(pool<dict<RTLIL::SigBit, bool>> &conditions, SigBit olden)
+	RTLIL::SigBit conditions_to_logic(std::set<std::map<RTLIL::SigBit, bool>> &conditions, SigBit olden, int &created_conditions)
 	{
 		auto key = make_pair(conditions, olden);
 
@@ -120,9 +123,10 @@ struct OptMemFeedbackWorker
 				sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0);
 			}
 			terms.append(module->Ne(NEW_ID, sig1, sig2));
+			created_conditions++;
 		}
 
-		if (olden != State::S1)
+		if (olden.wire != nullptr || olden != State::S1)
 			terms.append(olden);
 
 		if (GetSize(terms) == 0)
@@ -134,115 +138,120 @@ struct OptMemFeedbackWorker
 		return conditions_logic_cache[key] = terms;
 	}
 
-	void translate_rd_feedback_to_en(Mem &mem)
+	void translate_rd_feedback_to_en(std::string memid, std::vector<RTLIL::Cell*> &rd_ports, std::vector<RTLIL::Cell*> &wr_ports)
 	{
-		// Look for async read ports that may be suitable for feedback paths.
-		dict<RTLIL::SigSpec, std::vector<pool<RTLIL::SigBit>>> async_rd_bits;
+		std::map<RTLIL::SigSpec, std::vector<std::set<RTLIL::SigBit>>> async_rd_bits;
+		std::map<RTLIL::SigBit, std::set<RTLIL::SigBit>> muxtree_upstream_map;
+		std::set<RTLIL::SigBit> non_feedback_nets;
 
-		for (auto &port : mem.rd_ports)
+		for (auto wire : module->wires())
+			if (wire->port_output) {
+				std::vector<RTLIL::SigBit> bits = sigmap(wire);
+				non_feedback_nets.insert(bits.begin(), bits.end());
+			}
+
+		for (auto cell : module->cells())
 		{
-			if (port.clk_enable)
+			bool ignore_data_port = false;
+
+			if (cell->type.in(ID($mux), ID($pmux)))
+			{
+				std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
+				std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
+				std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
+				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
+
+				non_feedback_nets.insert(sig_s.begin(), sig_s.end());
+
+				for (int i = 0; i < int(sig_y.size()); i++) {
+					muxtree_upstream_map[sig_y[i]].insert(sig_a[i]);
+					for (int j = 0; j < int(sig_s.size()); j++)
+						muxtree_upstream_map[sig_y[i]].insert(sig_b[i + j*sig_y.size()]);
+				}
+
+				continue;
+			}
+
+			if (cell->type.in(ID($memwr), ID($memrd)) &&
+					cell->parameters.at(ID::MEMID).decode_string() == memid)
+				ignore_data_port = true;
+
+			for (auto conn : cell->connections())
+			{
+				if (ignore_data_port && conn.first == ID::DATA)
+					continue;
+				std::vector<RTLIL::SigBit> bits = sigmap(conn.second);
+				non_feedback_nets.insert(bits.begin(), bits.end());
+			}
+		}
+
+		std::set<RTLIL::SigBit> expand_non_feedback_nets = non_feedback_nets;
+		while (!expand_non_feedback_nets.empty())
+		{
+			std::set<RTLIL::SigBit> new_expand_non_feedback_nets;
+
+			for (auto &bit : expand_non_feedback_nets)
+				if (muxtree_upstream_map.count(bit))
+					for (auto &new_bit : muxtree_upstream_map.at(bit))
+						if (!non_feedback_nets.count(new_bit)) {
+							non_feedback_nets.insert(new_bit);
+							new_expand_non_feedback_nets.insert(new_bit);
+						}
+
+			expand_non_feedback_nets.swap(new_expand_non_feedback_nets);
+		}
+
+		for (auto cell : rd_ports)
+		{
+			if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
 				continue;
 
-			SigSpec addr = sigmap_xmux(port.addr);
+			RTLIL::SigSpec sig_addr = sigmap(cell->getPort(ID::ADDR));
+			std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort(ID::DATA));
 
-			async_rd_bits[addr].resize(mem.width);
-			for (int i = 0; i < mem.width; i++)
-				async_rd_bits[addr][i].insert(sigmap(port.data[i]));
+			for (int i = 0; i < int(sig_data.size()); i++)
+				if (non_feedback_nets.count(sig_data[i]))
+					goto not_pure_feedback_port;
+
+			async_rd_bits[sig_addr].resize(max(async_rd_bits.size(), sig_data.size()));
+			for (int i = 0; i < int(sig_data.size()); i++)
+				async_rd_bits[sig_addr][i].insert(sig_data[i]);
+
+		not_pure_feedback_port:;
 		}
 
 		if (async_rd_bits.empty())
 			return;
 
-		// Look for actual feedback paths.
-		std::vector<FeedbackPath> paths;
+		log("Populating enable bits on write ports of memory %s.%s with aync read feedback:\n", log_id(module), log_id(memid));
 
-		for (int i = 0; i < GetSize(mem.wr_ports); i++)
+		for (auto cell : wr_ports)
 		{
-			auto &port = mem.wr_ports[i];
-
-			SigSpec addr = sigmap_xmux(port.addr);
-
-			if (!async_rd_bits.count(addr))
+			RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort(ID::ADDR));
+			if (!async_rd_bits.count(sig_addr))
 				continue;
 
-			log("  Analyzing %s.%s write port %d.\n", log_id(module), log_id(mem.memid), i);
+			log("  Analyzing write port %s.\n", log_id(cell));
 
-			for (int j = 0; j < GetSize(port.data); j++)
-			{
-				if (port.en[j] == State::S0)
-					continue;
+			std::vector<RTLIL::SigBit> cell_data = cell->getPort(ID::DATA);
+			std::vector<RTLIL::SigBit> cell_en = cell->getPort(ID::EN);
 
-				dict<RTLIL::SigBit, bool> state;
+			int created_conditions = 0;
+			for (int i = 0; i < int(cell_data.size()); i++)
+				if (cell_en[i] != RTLIL::SigBit(RTLIL::State::S0))
+				{
+					std::map<RTLIL::SigBit, bool> state;
+					std::set<std::map<RTLIL::SigBit, bool>> conditions;
 
-				find_data_feedback(async_rd_bits.at(addr).at(j), sigmap(port.data[j]), state, i, j, paths);
+					find_data_feedback(async_rd_bits.at(sig_addr).at(i), cell_data[i], state, conditions);
+					cell_en[i] = conditions_to_logic(conditions, cell_en[i], created_conditions);
+				}
+
+			if (created_conditions) {
+				log("    Added enable logic for %d different cases.\n", created_conditions);
+				cell->setPort(ID::EN, cell_en);
 			}
 		}
-
-		if (paths.empty())
-			return;
-
-		// Now determine which read ports are actually used only for
-		// feedback paths, and can be removed.
-
-		dict<SigBit, int> feedback_users_count;
-		for (auto &path : paths)
-			feedback_users_count[path.feedback_bit]++;
-
-		pool<SigBit> feedback_ok;
-		for (auto &port : mem.rd_ports)
-		{
-			if (port.clk_enable)
-				continue;
-
-			bool ok = true;
-			for (auto bit : sigmap(port.data))
-				if (sig_users_count[bit] != feedback_users_count[bit])
-					ok = false;
-
-			if (ok)
-			{
-				// This port is going bye-bye.
-				for (auto bit : sigmap(port.data))
-					feedback_ok.insert(bit);
-
-				port.removed = true;
-			}
-		}
-
-		if (feedback_ok.empty())
-			return;
-
-		// Prepare a feedback condition list grouped by port bits.
-
-		dict<std::pair<int, int>, pool<dict<SigBit, bool>>> portbit_conds;
-		for (auto &path : paths)
-			if (feedback_ok.count(path.feedback_bit))
-				portbit_conds[std::make_pair(path.wrport_idx, path.data_bit_idx)].insert(path.condition);
-
-		if (portbit_conds.empty())
-			return;
-
-		// Okay, let's do it.
-
-		log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", log_id(module), log_id(mem.memid));
-
-		for (auto &it : portbit_conds)
-		{
-			int wrport_idx = it.first.first;
-			int bit = it.first.second;
-			auto &port = mem.wr_ports[wrport_idx];
-
-			port.en[bit] = conditions_to_logic(it.second, port.en[bit]);
-			log("    Port %d bit %d: added enable logic for %d different cases.\n", wrport_idx, bit, GetSize(it.second));
-		}
-
-		mem.emit();
-
-		for (auto bit : feedback_ok)
-			module->connect(bit, State::Sx);
-
-		design->scratchpad_set_bool("opt.did_something", true);
 	}
 
 	// -------------
@@ -253,7 +262,7 @@ struct OptMemFeedbackWorker
 
 	void operator()(RTLIL::Module* module)
 	{
-		std::vector<Mem> memories = Mem::get_selected_memories(module);
+		std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex;
 
 		this->module = module;
 		sigmap.set(module);
@@ -261,15 +270,14 @@ struct OptMemFeedbackWorker
 		conditions_logic_cache.clear();
 
 		sigmap_xmux = sigmap;
-
-		for (auto wire : module->wires()) {
-			if (wire->port_output)
-				for (auto bit : sigmap(wire))
-					sig_users_count[bit]++;
-		}
-
 		for (auto cell : module->cells())
 		{
+			if (cell->type == ID($memrd))
+				memindex[cell->parameters.at(ID::MEMID).decode_string()].first.push_back(cell);
+
+			if (cell->type == ID($memwr))
+				memindex[cell->parameters.at(ID::MEMID).decode_string()].second.push_back(cell);
+
 			if (cell->type == ID($mux))
 			{
 				RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
@@ -287,15 +295,13 @@ struct OptMemFeedbackWorker
 				for (int i = 0; i < int(sig_y.size()); i++)
 					sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
 			}
-
-			for (auto &conn : cell->connections())
-				if (!cell->known() || cell->input(conn.first))
-					for (auto bit : sigmap(conn.second))
-						sig_users_count[bit]++;
 		}
 
-		for (auto &mem : memories)
-			translate_rd_feedback_to_en(mem);
+		for (auto &it : memindex) {
+			std::sort(it.second.first.begin(), it.second.first.end(), memrd_cmp);
+			std::sort(it.second.second.begin(), it.second.second.end(), memwr_cmp);
+			translate_rd_feedback_to_en(it.first, it.second.first, it.second.second);
+		}
 	}
 };
 
@@ -307,10 +313,10 @@ struct OptMemFeedbackPass : public Pass {
 		log("\n");
 		log("    opt_mem_feedback [selection]\n");
 		log("\n");
-		log("This pass detects cases where an asynchronous read port is only connected via\n");
-		log("a mux tree to a write port with the same address.  When such a connection is\n");
-		log("found, it is replaced with a new condition on an enable signal, allowing\n");
-		log("for removal of the read port.\n");
+		log("This pass detects cases where an asynchronous read port is connected via\n");
+		log("a mux tree to a write port with the same address.  When such a path is\n");
+		log("found, it is replaced with a new condition on an enable signal, possibly\n");
+		log("allowing for removal of the read port.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {

tests/opt/bug2766.ys

@@ -1,101 +0,0 @@
-# Case 1.
-
-read_verilog << EOT
-
-module top(...);
-
-input clk;
-input sel;
-input [3:0] ra;
-input [3:0] wa;
-input wd;
-output [3:0] rd;
-
-reg [3:0] mem[0:15];
-
-integer i;
-initial begin
-        for (i = 0; i < 16; i = i + 1)
-                mem[i] <= i;
-end
-
-assign rd = mem[ra];
-
-always @(posedge clk) begin
-        mem[wa] <= {4{sel ? wd : mem[wa][0]}};
-end
-
-endmodule
-
-EOT
-
-hierarchy -auto-top
-proc
-opt_clean
-
-design -save start
-memory_map
-design -save preopt
-
-design -load start
-opt_mem_feedback
-memory_map
-design -save postopt
-
-equiv_opt -assert -run prepare: :
-
-
-
-design -reset
-
-# Case 2.
-
-read_verilog << EOT
-
-module top(...);
-
-input clk;
-input s1;
-input s2;
-input s3;
-input [3:0] ra;
-input [3:0] wa;
-input wd;
-output rd;
-
-reg mem[0:15];
-
-integer i;
-initial begin
-        for (i = 0; i < 16; i = i + 1)
-                mem[i] <= ^i;
-end
-
-assign rd = mem[ra];
-
-wire ta = s1 ? wd : mem[wa];
-wire tb = s2 ? wd : ta;
-wire tc = s3 ? tb : ta;
-
-always @(posedge clk) begin
-        mem[wa] <= tc;
-end
-
-endmodule
-
-EOT
-
-hierarchy -auto-top
-proc
-opt_clean
-
-design -save start
-memory_map
-design -save preopt
-
-design -load start
-opt_mem_feedback
-memory_map
-design -save postopt
-
-equiv_opt -assert -run prepare: :

tests/opt/opt_mem_feedback.ys

@@ -1,142 +0,0 @@
-# Good case: proper feedback port.
-
-read_verilog << EOT
-
-module top(...);
-
-input clk;
-input en;
-input s;
-
-input [3:0] ra;
-output [15:0] rd;
-input [3:0] wa;
-input [15:0] wd;
-
-reg [15:0] mem[0:15];
-
-assign rd = mem[ra];
-
-always @(posedge clk) begin
-	if (en) begin
-		mem[wa] <= {mem[wa][15:8], s ? wd[7:0] : mem[wa][7:0]};
-	end
-end
-
-endmodule
-
-EOT
-
-hierarchy -auto-top
-proc
-opt_clean
-
-design -save start
-memory_map
-design -save preopt
-
-design -load start
-opt_mem_feedback
-select -assert-count 1 t:$memrd
-memory_map
-design -save postopt
-
-equiv_opt -assert -run prepare: :
-
-
-
-design -reset
-
-# Bad case: read port also used for other things.
-
-read_verilog << EOT
-
-module top(...);
-
-input clk;
-input en;
-input s;
-
-output [15:0] rd;
-input [3:0] wa;
-input [15:0] wd;
-
-reg [15:0] mem[0:15];
-
-assign rd = mem[wa];
-
-always @(posedge clk) begin
-	if (en) begin
-		mem[wa] <= {s ? rd : wd[15:8], s ? wd[7:0] : rd};
-	end
-end
-
-endmodule
-
-EOT
-
-hierarchy -auto-top
-proc
-opt_clean
-
-design -save start
-memory_map
-design -save preopt
-
-design -load start
-select -assert-count 1 t:$memrd
-opt_mem_feedback
-select -assert-count 1 t:$memrd
-memory_map
-design -save postopt
-
-equiv_opt -assert -run prepare: :
-
-
-
-design -reset
-
-# Bad case: another user of the mux out.
-
-read_verilog << EOT
-
-module top(...);
-
-input clk;
-input en;
-input s;
-
-output [15:0] rd;
-input [3:0] wa;
-input [15:0] wd;
-
-reg [15:0] mem[0:15];
-
-assign rd = s ? wd : mem[wa];
-
-always @(posedge clk) begin
-	if (en) begin
-		mem[wa] <= rd;
-	end
-end
-
-endmodule
-
-EOT
-
-hierarchy -auto-top
-proc
-opt_clean
-
-design -save start
-memory_map
-design -save preopt
-
-design -load start
-select -assert-count 1 t:$memrd
-opt_mem_feedback
-select -assert-count 1 t:$memrd
-memory_map
-design -save postopt
-
-equiv_opt -assert -run prepare: :