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35082b0165
Author | SHA1 | Date |
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Catherine | 35082b0165 |
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@ -1,6 +1,5 @@
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#include "kernel/yosys.h"
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#include "kernel/yosys.h"
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#include "kernel/ff.h"
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#include "kernel/ff.h"
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#include "libparse.h"
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#include <optional>
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#include <optional>
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USING_YOSYS_NAMESPACE
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USING_YOSYS_NAMESPACE
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@ -11,7 +10,6 @@ struct ClockGateCell {
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IdString ce_pin;
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IdString ce_pin;
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IdString clk_in_pin;
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IdString clk_in_pin;
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IdString clk_out_pin;
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IdString clk_out_pin;
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std::vector<IdString> tie_lo_pins;
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};
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};
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ClockGateCell icg_from_arg(std::string& name, std::string& str) {
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ClockGateCell icg_from_arg(std::string& name, std::string& str) {
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@ -39,166 +37,6 @@ ClockGateCell icg_from_arg(std::string& name, std::string& str) {
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return c;
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return c;
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}
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}
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static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
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find_icgs(std::string filename, std::vector<std::string> const& dont_use_cells) {
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std::ifstream f;
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f.open(filename.c_str());
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if (f.fail())
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log_cmd_error("Can't open liberty file `%s': %s\n", filename.c_str(), strerror(errno));
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LibertyParser libparser(f);
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f.close();
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auto ast = libparser.ast;
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// We will pick the most suitable ICG absed on tie_lo count and area
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struct ICGRankable : public ClockGateCell { double area; };
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std::optional<ICGRankable> best_pos;
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std::optional<ICGRankable> best_neg;
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if (ast->id != "library")
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log_error("Format error in liberty file.\n");
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// This is a lot of boilerplate, isn't it?
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for (auto cell : ast->children)
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{
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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const LibertyAst *dn = cell->find("dont_use");
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if (dn != nullptr && dn->value == "true")
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continue;
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bool dont_use = false;
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for (auto dont_use_cell : dont_use_cells)
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{
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if (patmatch(dont_use_cell.c_str(), cell->args[0].c_str()))
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{
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dont_use = true;
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break;
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}
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}
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if (dont_use)
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continue;
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const LibertyAst *icg_kind_ast = cell->find("clock_gating_integrated_cell");
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if (icg_kind_ast == nullptr)
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continue;
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auto cell_name = cell->args[0];
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auto icg_kind = icg_kind_ast->value;
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auto starts_with = [&](std::string prefix) {
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return icg_kind.compare(0, prefix.size(), prefix) == 0;
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};
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bool clk_pol;
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if (icg_kind == "latch_posedge" || starts_with("latch_posedge_")) {
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clk_pol = true;
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} else if (icg_kind == "latch_negedge" || starts_with("latch_negedge_")) {
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clk_pol = false;
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} else {
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log("Ignoring ICG primitive %s of kind '%s'\n", cell_name.c_str(), icg_kind.c_str());
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continue;
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}
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log_debug("maybe valid icg: %s\n", cell_name.c_str());
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ClockGateCell icg_interface;
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icg_interface.name = RTLIL::escape_id(cell_name);
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for (auto pin : cell->children) {
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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if (auto clk = pin->find("clock_gate_clock_pin")) {
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if (!icg_interface.clk_in_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto gclk = pin->find("clock_gate_out_pin")) {
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if (!icg_interface.clk_out_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto en = pin->find("clock_gate_enable_pin")) {
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if (!icg_interface.ce_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto se = pin->find("clock_gate_test_pin")) {
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icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0]));
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} else {
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const LibertyAst *dir = pin->find("direction");
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if (dir->value == "internal")
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continue;
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log_warning("Malformed liberty file - extra pin %s in cell %s\n",
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pin->args[0].c_str(), cell_name.c_str());
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continue;
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}
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}
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if (icg_interface.clk_in_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_clock_pin in cell %s",
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cell_name.c_str());
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continue;
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}
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if (icg_interface.clk_out_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_out_pin in cell %s",
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cell_name.c_str());
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continue;
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}
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if (icg_interface.ce_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_enable_pin in cell %s",
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cell_name.c_str());
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continue;
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}
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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if (ar != nullptr && !ar->value.empty())
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area = atof(ar->value.c_str());
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std::optional<ICGRankable>& icg_to_beat = clk_pol ? best_pos : best_neg;
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bool winning = false;
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if (icg_to_beat) {
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log_debug("ties: %zu ? %zu\n", icg_to_beat->tie_lo_pins.size(),
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icg_interface.tie_lo_pins.size());
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log_debug("area: %f ? %f\n", icg_to_beat->area, area);
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// Prefer fewer test enables over area reduction (unlikely to matter)
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auto goal = std::make_pair(icg_to_beat->tie_lo_pins.size(), icg_to_beat->area);
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auto cost = std::make_pair(icg_interface.tie_lo_pins.size(), area);
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winning = cost < goal;
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if (winning)
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log_debug("%s beats %s\n", icg_interface.name.c_str(), icg_to_beat->name.c_str());
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} else {
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log_debug("%s is the first of its polarity\n", icg_interface.name.c_str());
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winning = true;
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}
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if (winning) {
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ICGRankable new_icg {icg_interface, area};
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icg_to_beat.emplace(new_icg);
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}
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}
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std::optional<ClockGateCell> pos;
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std::optional<ClockGateCell> neg;
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if (best_pos) {
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log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str());
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pos.emplace(*best_pos);
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}
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if (best_neg) {
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log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str());
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neg.emplace(*best_neg);
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}
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return std::make_pair(pos, neg);
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}
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struct ClockgatePass : public Pass {
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struct ClockgatePass : public Pass {
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ClockgatePass() : Pass("clockgate", "extract clock gating out of flip flops") { }
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ClockgatePass() : Pass("clockgate", "extract clock gating out of flip flops") { }
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void help() override {
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void help() override {
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@ -222,20 +60,12 @@ struct ClockgatePass : public Pass {
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log(" user-specified <celltype> ICG (integrated clock gating)\n");
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log(" user-specified <celltype> ICG (integrated clock gating)\n");
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log(" cell with ports named <ce>, <clk>, <gclk>.\n");
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log(" cell with ports named <ce>, <clk>, <gclk>.\n");
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log(" The ICG's clock enable pin must be active high.\n");
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log(" The ICG's clock enable pin must be active high.\n");
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log(" -liberty <filename>\n");
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log(" If specified, ICGs will be selected from the liberty file\n");
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log(" if available. Priority is given to cells with fewer tie_lo\n");
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log(" inputs and smaller size. This removes the need to manually\n");
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log(" specify -pos or -neg and -tie_lo.\n");
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log(" -dont_use <celltype>\n");
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log(" Cells <celltype> won't be considered when searching for ICGs\n");
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log(" in the liberty file specified by -liberty.\n");
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log(" -tie_lo <port_name>\n");
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log(" -tie_lo <port_name>\n");
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log(" Port <port_name> of the ICG will be tied to zero.\n");
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log(" Port <port_name> of the ICG will be tied to zero.\n");
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log(" Intended for DFT scan-enable pins.\n");
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log(" Intended for DFT scan-enable pins.\n");
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log(" -min_net_size <n>\n");
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log(" -min_net_size <n>\n");
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log(" Only transform sets of at least <n> eligible FFs.\n");
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log(" Only transform sets of at least <n> eligible FFs.\n");
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log(" \n");
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// log(" \n");
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}
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}
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// One ICG will be generated per ClkNetInfo
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// One ICG will be generated per ClkNetInfo
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@ -280,9 +110,7 @@ struct ClockgatePass : public Pass {
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std::optional<ClockGateCell> pos_icg_desc;
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std::optional<ClockGateCell> pos_icg_desc;
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std::optional<ClockGateCell> neg_icg_desc;
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std::optional<ClockGateCell> neg_icg_desc;
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std::vector<std::string> tie_lo_pins;
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std::vector<std::string> tie_lo_ports;
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std::string liberty_file;
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std::vector<std::string> dont_use_cells;
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int min_net_size = 0;
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int min_net_size = 0;
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size_t argidx;
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size_t argidx;
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@ -298,33 +126,13 @@ struct ClockgatePass : public Pass {
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neg_icg_desc = icg_from_arg(name, rest);
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neg_icg_desc = icg_from_arg(name, rest);
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}
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}
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if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) {
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if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) {
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tie_lo_pins.push_back(RTLIL::escape_id(args[++argidx]));
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tie_lo_ports.push_back(RTLIL::escape_id(args[++argidx]));
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}
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if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
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liberty_file = args[++argidx];
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rewrite_filename(liberty_file);
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}
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if (args[argidx] == "-dont_use" && argidx+1 < args.size()) {
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dont_use_cells.push_back(args[++argidx]);
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continue;
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}
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}
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if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
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if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
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min_net_size = atoi(args[++argidx].c_str());
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min_net_size = atoi(args[++argidx].c_str());
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}
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}
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}
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}
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if (!liberty_file.empty())
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std::tie(pos_icg_desc, neg_icg_desc) =
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find_icgs(liberty_file, dont_use_cells);
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else {
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for (auto pin : tie_lo_pins) {
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if (pos_icg_desc)
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pos_icg_desc->tie_lo_pins.push_back(pin);
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if (neg_icg_desc)
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neg_icg_desc->tie_lo_pins.push_back(pin);
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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pool<Cell*> ce_ffs;
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pool<Cell*> ce_ffs;
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@ -377,7 +185,7 @@ struct ClockgatePass : public Pass {
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gclk.new_net = module->addWire(NEW_ID);
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gclk.new_net = module->addWire(NEW_ID);
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icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
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icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
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// Tie low DFT ports like scan chain enable
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// Tie low DFT ports like scan chain enable
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for (auto port : matching_icg_desc->tie_lo_pins)
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for (auto port : tie_lo_ports)
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icg->setPort(port, Const(0, 1));
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icg->setPort(port, Const(0, 1));
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// Fix CE polarity if needed
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// Fix CE polarity if needed
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if (!clk.pol_ce) {
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if (!clk.pol_ce) {
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@ -1,4 +1,4 @@
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read_rtlil <<EOT
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read_ilang <<EOT
|
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autoidx 1
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autoidx 1
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module \top
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module \top
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wire output 1 \Y
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wire output 1 \Y
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@ -1,107 +0,0 @@
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library(test) {
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/* Integrated clock gating cells */
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cell (pos_small_tielo) {
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area : 1;
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clock_gating_integrated_cell : latch_posedge_precontrol;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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clock_gate_clock_pin : true;
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direction : input;
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}
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pin (CE) {
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clock_gate_enable_pin : true;
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direction : input;
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}
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pin (SE) {
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clock_gate_test_pin : true;
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direction : input;
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}
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}
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cell (pos_big) {
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area : 10;
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clock_gating_integrated_cell : latch_posedge;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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clock_gate_clock_pin : true;
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direction : input;
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}
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pin (CE) {
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clock_gate_enable_pin : true;
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direction : input;
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}
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}
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cell (pos_small) {
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area : 1;
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clock_gating_integrated_cell : latch_posedge;
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pin (GCLK) {
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clock_gate_out_pin : true;
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direction : output;
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}
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pin (CLK) {
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||||||
clock_gate_clock_pin : true;
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direction : input;
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}
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||||||
pin (CE) {
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||||||
clock_gate_enable_pin : true;
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direction : input;
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}
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}
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cell (neg_big) {
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area : 10;
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clock_gating_integrated_cell : latch_negedge;
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pin (GCLK) {
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||||||
clock_gate_out_pin : true;
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direction : output;
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}
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||||||
pin (CLK) {
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||||||
clock_gate_clock_pin : true;
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||||||
direction : input;
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|
||||||
}
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|
||||||
pin (CE) {
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|
||||||
clock_gate_enable_pin : true;
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|
||||||
direction : input;
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|
||||||
}
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|
||||||
}
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|
||||||
cell (neg_small_tielo) {
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|
||||||
area : 1;
|
|
||||||
clock_gating_integrated_cell : latch_negedge_precontrol;
|
|
||||||
pin (GCLK) {
|
|
||||||
clock_gate_out_pin : true;
|
|
||||||
direction : output;
|
|
||||||
}
|
|
||||||
pin (CLK) {
|
|
||||||
clock_gate_clock_pin : true;
|
|
||||||
direction : input;
|
|
||||||
}
|
|
||||||
pin (CE) {
|
|
||||||
clock_gate_enable_pin : true;
|
|
||||||
direction : input;
|
|
||||||
}
|
|
||||||
pin (SE) {
|
|
||||||
clock_gate_test_pin : true;
|
|
||||||
direction : input;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
cell (neg_small) {
|
|
||||||
area : 1;
|
|
||||||
clock_gating_integrated_cell : latch_negedge;
|
|
||||||
pin (GCLK) {
|
|
||||||
clock_gate_out_pin : true;
|
|
||||||
direction : output;
|
|
||||||
}
|
|
||||||
pin (CLK) {
|
|
||||||
clock_gate_clock_pin : true;
|
|
||||||
direction : input;
|
|
||||||
}
|
|
||||||
pin (CE) {
|
|
||||||
clock_gate_enable_pin : true;
|
|
||||||
direction : input;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
|
@ -61,7 +61,7 @@ clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
|
||||||
# falling edge clock flops don't get matched on -pos
|
# falling edge clock flops don't get matched on -pos
|
||||||
select -module dffe_00 -assert-count 0 t:\\pdk_icg
|
select -module dffe_00 -assert-count 0 t:\\pdk_icg
|
||||||
select -module dffe_01 -assert-count 0 t:\\pdk_icg
|
select -module dffe_01 -assert-count 0 t:\\pdk_icg
|
||||||
# rising edge clock flops do get matched on -pos
|
# falling edge clock flops do get matched on -pos
|
||||||
select -module dffe_10 -assert-count 1 t:\\pdk_icg
|
select -module dffe_10 -assert-count 1 t:\\pdk_icg
|
||||||
select -module dffe_11 -assert-count 1 t:\\pdk_icg
|
select -module dffe_11 -assert-count 1 t:\\pdk_icg
|
||||||
# if necessary, EN is inverted, since the given ICG
|
# if necessary, EN is inverted, since the given ICG
|
||||||
|
@ -79,10 +79,10 @@ select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
|
||||||
design -load before
|
design -load before
|
||||||
clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
|
clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
|
||||||
|
|
||||||
# falling edge clock flops do get matched on -neg
|
# rising edge clock flops don't get matched on -neg
|
||||||
select -module dffe_00 -assert-count 1 t:\\pdk_icg
|
select -module dffe_00 -assert-count 1 t:\\pdk_icg
|
||||||
select -module dffe_01 -assert-count 1 t:\\pdk_icg
|
select -module dffe_01 -assert-count 1 t:\\pdk_icg
|
||||||
# rising edge clock flops don't get matched on -neg
|
# rising edge clock flops do get matched on -neg
|
||||||
select -module dffe_10 -assert-count 0 t:\\pdk_icg
|
select -module dffe_10 -assert-count 0 t:\\pdk_icg
|
||||||
select -module dffe_11 -assert-count 0 t:\\pdk_icg
|
select -module dffe_11 -assert-count 0 t:\\pdk_icg
|
||||||
# if necessary, EN is inverted, since the given ICG
|
# if necessary, EN is inverted, since the given ICG
|
||||||
|
@ -193,55 +193,4 @@ select -assert-count 1 t:\\pdk_icg
|
||||||
|
|
||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
design -load before
|
# TODO test -tie_lo
|
||||||
clockgate -liberty clockgate.lib
|
|
||||||
|
|
||||||
# rising edge ICGs
|
|
||||||
select -module dffe_00 -assert-count 0 t:\\pos_small
|
|
||||||
select -module dffe_01 -assert-count 0 t:\\pos_small
|
|
||||||
|
|
||||||
select -module dffe_10 -assert-count 1 t:\\pos_small
|
|
||||||
select -module dffe_11 -assert-count 1 t:\\pos_small
|
|
||||||
|
|
||||||
# falling edge ICGs
|
|
||||||
select -module dffe_00 -assert-count 1 t:\\neg_small
|
|
||||||
select -module dffe_01 -assert-count 1 t:\\neg_small
|
|
||||||
|
|
||||||
select -module dffe_10 -assert-count 0 t:\\neg_small
|
|
||||||
select -module dffe_11 -assert-count 0 t:\\neg_small
|
|
||||||
|
|
||||||
# and nothing else
|
|
||||||
select -module dffe_00 -assert-count 0 t:\\pos_big
|
|
||||||
select -module dffe_01 -assert-count 0 t:\\pos_big
|
|
||||||
select -module dffe_10 -assert-count 0 t:\\pos_big
|
|
||||||
select -module dffe_11 -assert-count 0 t:\\pos_big
|
|
||||||
select -module dffe_00 -assert-count 0 t:\\pos_small_tielo
|
|
||||||
select -module dffe_01 -assert-count 0 t:\\pos_small_tielo
|
|
||||||
select -module dffe_10 -assert-count 0 t:\\pos_small_tielo
|
|
||||||
select -module dffe_11 -assert-count 0 t:\\pos_small_tielo
|
|
||||||
select -module dffe_00 -assert-count 0 t:\\neg_big
|
|
||||||
select -module dffe_01 -assert-count 0 t:\\neg_big
|
|
||||||
select -module dffe_10 -assert-count 0 t:\\neg_big
|
|
||||||
select -module dffe_11 -assert-count 0 t:\\neg_big
|
|
||||||
select -module dffe_00 -assert-count 0 t:\\neg_small_tielo
|
|
||||||
select -module dffe_01 -assert-count 0 t:\\neg_small_tielo
|
|
||||||
select -module dffe_10 -assert-count 0 t:\\neg_small_tielo
|
|
||||||
select -module dffe_11 -assert-count 0 t:\\neg_small_tielo
|
|
||||||
|
|
||||||
# if necessary, EN is inverted, since the given ICG
|
|
||||||
# is assumed to have an active-high EN
|
|
||||||
select -module dffe_10 -assert-count 1 t:\$_NOT_
|
|
||||||
select -module dffe_11 -assert-count 0 t:\$_NOT_
|
|
||||||
|
|
||||||
#------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
design -load before
|
|
||||||
clockgate -liberty clockgate.lib -dont_use pos_small -dont_use neg_small
|
|
||||||
|
|
||||||
# rising edge ICGs
|
|
||||||
select -module dffe_10 -assert-count 1 t:\\pos_big
|
|
||||||
select -module dffe_11 -assert-count 1 t:\\pos_big
|
|
||||||
|
|
||||||
# falling edge ICGs
|
|
||||||
select -module dffe_00 -assert-count 1 t:\\neg_big
|
|
||||||
select -module dffe_01 -assert-count 1 t:\\neg_big
|
|
||||||
|
|
Loading…
Reference in New Issue