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2 Commits
7484cce42a ... d69b4a3b6a

Author SHA1 Message Date
Martin Povišer d69b4a3b6a
Merge 6f7f71fe03 into 1184418cc8 2024-11-20 13:14:17 +01:00
Martin Povišer 6f7f71fe03 read_blif: Represent sequential elements with gate cells 
When reading the BLIF input, represent the native sequential elements
with fine-grained cells like `$_FF_` instead of the coarse-grained cells
like `$ff` which we were using up to now.

There are two reasons for this:

 * The sequential elements in BLIF are always single-bit, so the gate
   cells are a better fit.

 * This makes it symmetrical to the BLIF backend which only understands
   the fine-grained cells, and only translates those to the native BLIF
   features.
 2024-01-09 19:31:44 +01:00
1 changed files with 5 additions and 5 deletions
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10
frontends/blif/blifparse.cc
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@ -362,17 +362,17 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto no_latch_clock; goto no_latch_clock;
if (!strcmp(edge, "re")) if (!strcmp(edge, "re"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); cell = module->addDffGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "fe")) else if (!strcmp(edge, "fe"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); cell = module->addDffGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else if (!strcmp(edge, "ah")) else if (!strcmp(edge, "ah"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); cell = module->addDlatchGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "al")) else if (!strcmp(edge, "al"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); cell = module->addDlatchGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else { else {
no_latch_clock: no_latch_clock:
if (dff_name.empty()) { if (dff_name.empty()) {
cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q)); cell = module->addFfGate(NEW_ID, blif_wire(d), blif_wire(q));
} else { } else {
cell = module->addCell(NEW_ID, dff_name); cell = module->addCell(NEW_ID, dff_name);
cell->setPort(ID::D, blif_wire(d)); cell->setPort(ID::D, blif_wire(d));