More deadname stuff

git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed

s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;

Makefile

@@ -956,7 +956,7 @@ ifeq ($(ENABLE_ABC),1)
 	cp -r $(PROGRAM_PREFIX)yosys-abc.exe abc/lib/x86/pthreadVC2.dll yosys-win32-mxebin-$(YOSYS_VER)/
 endif
 	echo -en 'This is Yosys $(YOSYS_VER) for Win32.\r\n' > yosys-win32-mxebin-$(YOSYS_VER)/readme.txt
-	echo -en 'Documentation at http://yosyshq.net/yosys/.\r\n' >> yosys-win32-mxebin-$(YOSYS_VER)/readme.txt
+	echo -en 'Documentation at https://yosyshq.net/yosys/.\r\n' >> yosys-win32-mxebin-$(YOSYS_VER)/readme.txt
 	zip -r yosys-win32-mxebin-$(YOSYS_VER).zip yosys-win32-mxebin-$(YOSYS_VER)/
 endif
 

README.md

@@ -38,11 +38,11 @@ Web Site and Other Resources
 ============================
 
 More information and documentation can be found on the Yosys web site:
-- http://yosyshq.net/yosys/
+- https://yosyshq.net/yosys/
 
 The "Documentation" page on the web site contains links to more resources,
 including a manual that even describes some of the Yosys internals:
-- http://yosyshq.net/yosys/documentation.html
+- https://yosyshq.net/yosys/documentation.html
 
 The directory `guidelines` contains additional information
 for people interested in using the Yosys C++ APIs.
@@ -92,7 +92,7 @@ For Cygwin use the following command to install all prerequisites, or select the
 
 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
 as a source distribution for Visual Studio. Visit the Yosys download page for
-more information: http://yosyshq.net/yosys/download.html
+more information: https://yosyshq.net/yosys/download.html
 
 To configure the build system to use a specific compiler, use one of
 
@@ -568,7 +568,7 @@ Building the documentation
 ==========================
 
 Note that there is no need to build the manual if you just want to read it.
-Simply download the PDF from http://yosyshq.net/yosys/documentation.html
+Simply download the PDF from https://yosyshq.net/yosys/documentation.html
 instead.
 
 On Ubuntu, texlive needs these packages to be able to build the manual:

manual/APPNOTE_010_Verilog_to_BLIF.tex

@@ -52,7 +52,7 @@
 \begin{document}
 
 \title{Yosys Application Note 010: \\ Converting Verilog to BLIF}
-\author{Clifford Wolf \\ November 2013}
+\author{Claire Xenia Wolf \\ November 2013}
 \maketitle
 
 \begin{abstract}
@@ -437,12 +437,12 @@ design to fit a certain need without actually touching the RTL code.
 \begin{thebibliography}{9}
 
 \bibitem{yosys}
-Clifford Wolf. The Yosys Open SYnthesis Suite. \\
-\url{http://yosyshq.net/yosys/}
+Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\
+\url{https://yosyshq.net/yosys/}
 
 \bibitem{bigsim}
 yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\
-\url{https://github.com/cliffordwolf/yosys-bigsim}
+\url{https://github.com/YosysHQ/yosys-bigsim}
 
 \bibitem{navre}
 Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\

manual/APPNOTE_011_Design_Investigation.tex

@@ -54,7 +54,7 @@
 \begin{document}
 
 \title{Yosys Application Note 011: \\ Interactive Design Investigation}
-\author{Clifford Wolf \\ Original Version December 2013}
+\author{Claire Xenia Wolf \\ Original Version December 2013}
 \maketitle
 
 \begin{abstract}
@@ -1041,8 +1041,8 @@ framework for new algorithms alike.
 \begin{thebibliography}{9}
 
 \bibitem{yosys}
-Clifford Wolf. The Yosys Open SYnthesis Suite.
-\url{http://yosyshq.net/yosys/}
+Claire Xenia Wolf. The Yosys Open SYnthesis Suite.
+\url{https://yosyshq.net/yosys/}
 
 \bibitem{graphviz}
 Graphviz - Graph Visualization Software.

manual/APPNOTE_012_Verilog_to_BTOR.tex

@@ -52,7 +52,7 @@
 \begin{document}
 
 \title{Yosys Application Note 012: \\ Converting Verilog to BTOR}
-\author{Ahmed Irfan and Clifford Wolf \\ April 2015}
+\author{Ahmed Irfan and Claire Xenia Wolf \\ April 2015}
 \maketitle
 
 \begin{abstract}
@@ -410,8 +410,8 @@ verification benchmarks with or without memories from Verilog designs.
 \begin{thebibliography}{9}
 
 \bibitem{yosys}
-Clifford Wolf. The Yosys Open SYnthesis Suite. \\
-\url{http://yosyshq.net/yosys/}
+Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\
+\url{https://yosyshq.net/yosys/}
 
 \bibitem{boolector}
 Robert Brummayer and Armin Biere, Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays\\

manual/CHAPTER_Auxlibs.tex

@@ -22,7 +22,7 @@ ConstEval} class provided in {\tt kernel/consteval.h}.
 \label{sec:SubCircuit}
 
 The files in {\tt libs/subcircuit} provide a library for solving the subcircuit
-isomorphism problem. It is written by Clifford Wolf and based on the Ullmann
+isomorphism problem. It is written by C. Wolf and based on the Ullmann
 Subgraph Isomorphism Algorithm \cite{UllmannSubgraphIsomorphism}. It is used by
 the {\tt extract} pass (see {\tt help extract} or Sec.~\ref{cmd:extract}).
 
@@ -30,6 +30,6 @@ the {\tt extract} pass (see {\tt help extract} or Sec.~\ref{cmd:extract}).
 
 The files in {\tt libs/ezsat} provide a library for simplifying generating CNF
 formulas for SAT solvers. It also contains bindings of MiniSAT. The ezSAT
-library is written by Clifford Wolf. It is used by the {\tt sat} pass (see
+library is written by C. Wolf. It is used by the {\tt sat} pass (see
 {\tt help sat} or Sec.~\ref{cmd:sat}).
 

manual/PRESENTATION_ExAdv.tex

@@ -890,7 +890,7 @@ Questions?
 \bigskip
 \bigskip
 \begin{center}
-\url{http://yosyshq.net/yosys/}
+\url{https://yosyshq.net/yosys/}
 \end{center}
 \end{frame}
 

manual/PRESENTATION_ExOth.tex

@@ -221,7 +221,7 @@ Questions?
 \bigskip
 \bigskip
 \begin{center}
-\url{http://yosyshq.net/yosys/}
+\url{https://yosyshq.net/yosys/}
 \end{center}
 \end{frame}
 

manual/PRESENTATION_ExSyn.tex

@@ -509,7 +509,7 @@ Questions?
 \bigskip
 \bigskip
 \begin{center}
-\url{http://yosyshq.net/yosys/}
+\url{https://yosyshq.net/yosys/}
 \end{center}
 \end{frame}
 

manual/PRESENTATION_Intro.tex

@@ -260,7 +260,7 @@ The following slides cover an example project. This project contains three files
 \end{itemize}
 \vfill
 Direct link to the files: \\ \footnotesize
-\url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro}
+\url{https://github.com/YosysHQ/yosys/tree/master/manual/PRESENTATION_Intro}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -476,7 +476,7 @@ Command reference:
 \begin{itemize}
 \item Use ``{\tt help}'' for a command list and ``{\tt help \it command}'' for details.
 \item Or run ``{\tt yosys -H}'' or ``{\tt yosys -h \it command}''.
-\item Or go to \url{http://yosyshq.net/yosys/documentation.html}.
+\item Or go to \url{https://yosyshq.net/yosys/documentation.html}.
 \end{itemize}
 
 \bigskip
@@ -806,7 +806,7 @@ but also formal verification, reverse engineering, ...}
 \begin{itemize}
 \item Ongoing PhD project on coarse grain synthesis \\
 {\setlength{\parindent}{0.5cm}\footnotesize
-Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect
+Johann Glaser and C. Wolf. Methodology and Example-Driven Interconnect
 Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
 Architectures. In Jan Haase, editor, \it Models, Methods, and Tools for Complex
 Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp
@@ -913,11 +913,11 @@ control logic because it is simpler than setting up a commercial flow.
 \begin{frame}{\subsecname}
 \begin{itemize}
 \item Website: \\
-\smallskip\hskip1cm\url{http://yosyshq.net/yosys/}
+\smallskip\hskip1cm\url{https://yosyshq.net/yosys/}
 
 \bigskip
 \item Manual, Command Reference, Application Notes: \\
-\smallskip\hskip1cm\url{http://yosyshq.net/yosys/documentation.html}
+\smallskip\hskip1cm\url{https://yosyshq.net/yosys/documentation.html}
 
 \bigskip
 \item Instead of a mailing list we have a SubReddit: \\
@@ -925,7 +925,7 @@ control logic because it is simpler than setting up a commercial flow.
 
 \bigskip
 \item Direct link to the source code: \\
-\smallskip\hskip1cm\url{https://github.com/cliffordwolf/yosys}
+\smallskip\hskip1cm\url{https://github.com/YosysHQ/yosys}
 \end{itemize}
 \end{frame}
 
@@ -950,7 +950,7 @@ Questions?
 \bigskip
 \bigskip
 \begin{center}
-\url{http://yosyshq.net/yosys/}
+\url{https://yosyshq.net/yosys/}
 \end{center}
 \end{frame}
 

manual/PRESENTATION_Prog.tex

@@ -590,7 +590,7 @@ Questions?
 \bigskip
 \bigskip
 \begin{center}
-\url{http://yosyshq.net/yosys/}
+\url{https://yosyshq.net/yosys/}
 \end{center}
 \end{frame}
 

manual/literature.bib

@@ -1,7 +1,7 @@
 
 @inproceedings{intersynth,
 	title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},
-	author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},
+	author={C. Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},
 	booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},
 	pages={194--201},
 	year={2012}
@@ -9,7 +9,7 @@
 
 @incollection{intersynthFdlBookChapter,
 	title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},
-	author={Johann Glaser and Clifford Wolf},
+	author={Johann Glaser and C. Wolf},
 	booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12},
 	editor={Jan Haase},
 	publisher={Springer},
@@ -18,14 +18,14 @@
 }
 
 @unpublished{BACC,
-	author = {Clifford Wolf},
+	author = {C. Wolf},
 	title = {Design and Implementation of the Yosys Open SYnthesis Suite},
 	note = {Bachelor Thesis, Vienna University of Technology},
 	year = {2013}
 }
 
 @unpublished{VerilogFossEval,
-	author = {Clifford Wolf},
+	author = {C. Wolf},
 	title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility},
 	note = {Unpublished Student Research Paper, Vienna University of Technology},
 	year = {2012}

manual/manual.tex

@@ -51,7 +51,7 @@
 % Hyperlinks
 \usepackage[colorlinks,hyperindex,plainpages=false,%
 pdftitle={Yosys Manual},%
-pdfauthor={Clifford Wolf},%
+pdfauthor={Claire Xenia Wolf},%
 %pdfkeywords={keyword},%
 pdfpagelabels,%
 pagebackref,%
@@ -137,7 +137,7 @@ bookmarksopen=false%
 \bf\Huge Yosys Manual
 
 \bigskip
-\large Clifford Wolf
+\large Claire Xenia Wolf
 \end{center}
 
 \vfil\null

manual/presentation.tex

@@ -80,8 +80,8 @@
 \end{centering}}
 
 \title{Yosys Open SYnthesis Suite}
-\author{Clifford Wolf}
-\institute{http://yosyshq.net/yosys/}
+\author{Claire Xenia Wolf}
+\institute{https://yosyshq.net/yosys/}
 
 \usetheme{Madrid}
 \usecolortheme{seagull}
@@ -124,7 +124,7 @@ writing extensions to Yosys using the C++ API.
 
 \section{About me}
 \begin{frame}{About me}
-Hi! I'm Clifford Wolf.
+Hi! I'm Claire Xenia Wolf.
 
 \bigskip
 I like writing open source software. For example:

manual/weblinks.bib

@@ -1,20 +1,20 @@
 
 @misc{YosysGit,
-	author =       	{Clifford Wolf},
+	author =       	{Claire Xenia Wolf},
 	title =        	{{Yosys Open SYnthesis Suite (YOSYS)}},
-	note =		{\url{http://github.com/cliffordwolf/yosys}}
+	note =		{\url{http://github.com/YosysHQ/yosys}}
 }
 
 @misc{YosysTestsGit,
-	author =       	{Clifford Wolf},
+	author =       	{Claire Xenia Wolf},
 	title =        	{{Yosys Test Bench}},
-	note =		{\url{http://github.com/cliffordwolf/yosys-tests}}
+	note =		{\url{http://github.com/YosysHQ/yosys-tests}}
 }
 
 @misc{VlogHammer,
-	author =       	{Clifford Wolf},
+	author =       	{Claire Xenia Wolf},
 	title =        	{{VlogHammer Verilog Synthesis Regression Tests}},
-	note =		{\url{http://github.com/cliffordwolf/VlogHammer}}
+	note =		{\url{http://github.com/YosysHQ/VlogHammer}}
 }
 
 @misc{Icarus,

misc/create_vcxsrc.sh

@@ -6,7 +6,7 @@ yosysver="$2"
 gitsha="$3"
 
 rm -rf YosysVS-Tpl-v2.zip YosysVS
-wget http://yosyshq.net/yosys/nogit/YosysVS-Tpl-v2.zip
+wget https://yosyshq.net/yosys/nogit/YosysVS-Tpl-v2.zip
 
 unzip YosysVS-Tpl-v2.zip
 rm -f YosysVS-Tpl-v2.zip

passes/sat/eval.cc

@@ -18,7 +18,7 @@
  */
 
 // [[CITE]] VlogHammer Verilog Regression Test Suite
-// http://yosyshq.net/yosys/vloghammer.html
+// https://yosyshq.net/yosys/vloghammer.html
 
 #include "kernel/register.h"
 #include "kernel/celltypes.h"

techlibs/common/mul2dsp.v

@@ -3,7 +3,7 @@
  *
  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *                2019  Eddie Hung    <eddie@fpgeh.com>
- *                2019  David Shah <dave@ds0.me>
+ *                2019  gatecat <gatecat@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

techlibs/ecp5/arith_map.v

@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

techlibs/ecp5/ecp5_gsr.cc

@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2019  David Shah <dave@ds0.me>
+ *  Copyright (C) 2019  gatecat <gatecat@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

techlibs/ecp5/synth_ecp5.cc

@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2018 David Shah <dave@ds0.me>
+ *  Copyright (C) 2018 gatecat <gatecat@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

techlibs/gowin/arith_map.v

@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

techlibs/nexus/arith_map.v

@@ -2,7 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
- *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

techlibs/nexus/synth_nexus.cc

@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2020 David Shah <dave@ds0.me>
+ *  Copyright (C) 2020 gatecat <gatecat@ds0.me>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

tests/simple/vloghammer.v

@@ -1,6 +1,6 @@
 
 // test cases found using vloghammer
-// https://github.com/cliffordwolf/VlogHammer
+// https://github.com/YosysHQ/VlogHammer
 
 module test01(a, y);
   input [7:0] a;

tests/vloghtb/run-test.sh

@@ -3,7 +3,7 @@
 set -ex
 
 rm -rf Makefile refdat rtl scripts spec
-wget -N http://yosyshq.net/yosys/nogit/vloghammer_tb.tar.bz2
+wget -N https://yosyshq.net/yosys/nogit/vloghammer_tb.tar.bz2
 tar --strip=1 -xjf vloghammer_tb.tar.bz2
 
 make clean