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7 Commits
50bc8c8e4d ... fd32b58502

Author SHA1 Message Date
KrystalDelusion fd32b58502
Merge 260cc42c2f into 29e8812bab 2024-11-26 04:07:22 +13:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Miodrag Milanović 9512ec4bbc
Merge pull request #4764 from YosysHQ/micko/verific_vhdl_assert 
verific : VHDL assert DFF initial value set on Verific library patch
 2024-11-25 15:06:36 +01:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Krystine Sherwin 260cc42c2f
rtlil.cc: Fix decode for empty string 2024-06-10 14:32:42 +12:00
Krystine Sherwin 94b44a37b2
rtlil.cc: Fix #4427 
If a `RTLIL::Const` is composed of multiple strings, such as when using a ternary expression to select between two strings of different lengths, zero padding for the strings needs to be maintained.
Only leading (and trailing) null characters should be dropped from the decoded string, rather than all null characters.
 2024-06-10 14:18:49 +12:00
3 changed files with 31 additions and 11 deletions
Show Stats Expand all files Collapse all files

7
frontends/verific/verific.cc
View File

@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log(" assert condition %s.\n", log_signal(cond));
Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
// Initialize FF feeding condition to 1, in case it is not
// used by rest of design logic, to prevent failing on
// initial uninitialized state
if (cond.is_wire() && !cond.wire->name.isPublic())
cond.wire->attributes[ID::init] = Const(1,1);
import_attributes(cell->attributes, inst);
continue;
}
@ -3428,6 +3422,7 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1);
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
RuntimeFlags::SetVar("veri_create_empty_box", 1);
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

11
kernel/rtlil.cc
View File

@ -480,8 +480,7 @@ std::string RTLIL::Const::decode_string() const
ch |= 1 << j;
}
}
if (ch != 0)
s.append({ch});
s.append({ch});
}
i -= 8;
for (; i >= 0; i -= 8) {
@ -491,10 +490,12 @@ std::string RTLIL::Const::decode_string() const
ch |= 1 << j;
}
}
if (ch != 0)
s.append({ch});
s.append({ch});
}
return s;
auto first_char = s.find_first_not_of('\0');
if (first_char != std::string::npos)
return s.substr(first_char);
else return s;
}
int RTLIL::Const::size() const {

24
tests/verific/blackbox.ys Normal file
View File

@ -0,0 +1,24 @@
verific -sv -lib <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
always @(posedge clk) begin
if (PATH=="DEFAULT")
c <= a;
else
c <= b;
end
endmodule
EOF
verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF
verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL