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6 Commits
4d05e9b323 ... 60cab78960

Author SHA1 Message Date
Martin Povišer 60cab78960
Merge 6f7f71fe03 into 29e8812bab 2024-11-25 15:54:12 +01:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Miodrag Milanović 9512ec4bbc
Merge pull request #4764 from YosysHQ/micko/verific_vhdl_assert 
verific : VHDL assert DFF initial value set on Verific library patch
 2024-11-25 15:06:36 +01:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Martin Povišer 6f7f71fe03 read_blif: Represent sequential elements with gate cells 
When reading the BLIF input, represent the native sequential elements
with fine-grained cells like `$_FF_` instead of the coarse-grained cells
like `$ff` which we were using up to now.

There are two reasons for this:

 * The sequential elements in BLIF are always single-bit, so the gate
   cells are a better fit.

 * This makes it symmetrical to the BLIF backend which only understands
   the fine-grained cells, and only translates those to the native BLIF
   features.
 2024-01-09 19:31:44 +01:00
3 changed files with 30 additions and 11 deletions
Show Stats Expand all files Collapse all files

10
frontends/blif/blifparse.cc
View File

@ -362,17 +362,17 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto no_latch_clock;
if (!strcmp(edge, "re"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
cell = module->addDffGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "fe"))
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
cell = module->addDffGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else if (!strcmp(edge, "ah"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
cell = module->addDlatchGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
else if (!strcmp(edge, "al"))
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
cell = module->addDlatchGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
else {
no_latch_clock:
if (dff_name.empty()) {
cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
cell = module->addFfGate(NEW_ID, blif_wire(d), blif_wire(q));
} else {
cell = module->addCell(NEW_ID, dff_name);
cell->setPort(ID::D, blif_wire(d));

7
frontends/verific/verific.cc
View File

@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log(" assert condition %s.\n", log_signal(cond));
Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
// Initialize FF feeding condition to 1, in case it is not
// used by rest of design logic, to prevent failing on
// initial uninitialized state
if (cond.is_wire() && !cond.wire->name.isPublic())
cond.wire->attributes[ID::init] = Const(1,1);
import_attributes(cell->attributes, inst);
continue;
}
@ -3428,6 +3422,7 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1);
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
RuntimeFlags::SetVar("veri_create_empty_box", 1);
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

24
tests/verific/blackbox.ys Normal file
View File

@ -0,0 +1,24 @@
verific -sv -lib <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
always @(posedge clk) begin
if (PATH=="DEFAULT")
c <= a;
else
c <= b;
end
endmodule
EOF
verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF
verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL