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riscv:yosys-0.2.0

1 Commits
377f26e1f1 ... a5925cb837

Author SHA1 Message Date
George Rennie a5925cb837
Merge 583eb1addb into b89bd027a0 2024-11-19 14:24:46 +01:00
12 changed files with 122 additions and 4504 deletions
Show Stats Expand all files Collapse all files

2
libs/ezsat/demo_cmp.cc
View File

@ -19,7 +19,6 @@
#include "ezminisat.h"
#include <assert.h>
#include <stdlib.h>
#define INIT_X 123456789
#define INIT_Y 362436069
@ -144,3 +143,4 @@ int main()
}
return 0;
}

2
libs/ezsat/demo_vec.cc
View File

@ -19,7 +19,6 @@
#include "ezminisat.h"
#include <assert.h>
#include <stdlib.h>
#define INIT_X 123456789
#define INIT_Y 362436069
@ -110,3 +109,4 @@ int main()
return 0;
}

5
misc/py_wrap_generator.py
View File

@ -1273,11 +1273,6 @@ class WFunction:
func.duplicate = False
func.namespace = namespace
str_def = str_def.replace("operator ","operator")
# remove attributes from the start
if str.startswith(str_def, "[[") and "]]" in str_def:
str_def = str_def[str_def.find("]]")+2:]
if str.startswith(str_def, "static "):
func.is_static = True
str_def = str_def[7:]

4
passes/opt/opt_demorgan.cc
View File

@ -39,10 +39,6 @@ void demorgan_worker(
return;
auto insig = sigmap(cell->getPort(ID::A));
if (GetSize(insig) < 1)
return;
log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++)

3
passes/opt/opt_reduce.cc
View File

@ -89,9 +89,6 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify();
if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;

5
passes/pmgen/peepopt_shiftadd.pmg
View File

@ -53,11 +53,6 @@ match add
select port(add, constport).is_fully_const()
define <IdString> varport (constport == \A ? \B : \A)
// only optimize for constants up to a fixed width. this prevents cases
// with a blowup in internal term size and prevents larger constants being
// casted to int incorrectly
select (GetSize(port(add, constport)) <= 24)
// if a value of var is able to wrap the output, the transformation might give wrong results
// an addition/substraction can at most flip one more bit than the largest operand (the carry bit)
// as long as the output can show this bit, no wrap should occur (assuming all signed-ness make sense)

4
passes/proc/proc_dff.cc
View File

@ -262,7 +262,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
{
log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
continue;
return;
}
// If there is a reset condition in the async rules, use it
@ -277,7 +277,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
sync_edge->type == RTLIL::SyncType::STp,
sync_level && sync_level->type == RTLIL::SyncType::ST1,
sync_edge->signal, sync_level->signal, proc);
continue;
return;
}
gen_dff(mod, insig, rstval.as_const(), sig_q,

2
techlibs/gowin/cells_xtra.py
View File

@ -65,8 +65,6 @@ if __name__ == '__main__':
dirs = [
os.path.join(args.gowin_dir, 'IDE/simlib/gw1n/'),
os.path.join(args.gowin_dir, 'IDE/simlib/gw2a/'),
os.path.join(args.gowin_dir, 'IDE/simlib/gw5a/'),
]
with open('cells_xtra.v', 'w') as fout:

4539
techlibs/gowin/cells_xtra.v
View File

File diff suppressed because it is too large Load Diff

15
tests/opt/bug4610.ys
View File

@ -1,15 +0,0 @@
read_ilang <<EOT
autoidx 1
module \top
wire output 1 \Y
cell $reduce_or $reduce_or$rtl.v:29$20
parameter \A_SIGNED 0
parameter \A_WIDTH 0
parameter \Y_WIDTH 1
connect \A { }
connect \Y \Y
end
end
EOT
equiv_opt -assert opt_demorgan

14
tests/opt/opt_reduce_andor.ys
View File

@ -1,14 +0,0 @@
# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
read_verilog <<EOT
module reduce_const(output wire o, output wire a);
wire [3:0] zero = 4'b0000;
wire [3:0] ones = 4'b1111;
assign o = |zero;
assign a = &ones;
endmodule
EOT
equiv_opt -assert opt_reduce
design -load postopt
select -assert-none r:A_WIDTH=0

31
tests/proc/bug4712.ys
View File

@ -1,31 +0,0 @@
read_rtlil <<EOT
autoidx 1
module \top
wire input 1 \clk
wire input 2 \rst
wire input 3 \a_r
wire input 4 \a_n
wire input 5 \b_n
wire \a
wire \b
process $proc
sync high \rst
update \a \a_r
update \b \b
sync posedge \clk
update \a \a_n
update \b \b_n
end
end
EOT
proc_dff
proc_clean
# Processes should have been converted to one aldff and one dff
select -assert-none p:*
select -assert-count 1 t:$aldff
select -assert-count 1 t:$dff