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8 Commits
121c01f058 ... 9e48df6b4b

Author SHA1 Message Date
Carlo Alberto Ferraris 9e48df6b4b
Merge d67989f9ad into 29e8812bab 2024-11-25 15:54:12 +01:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Miodrag Milanović 9512ec4bbc
Merge pull request #4764 from YosysHQ/micko/verific_vhdl_assert 
verific : VHDL assert DFF initial value set on Verific library patch
 2024-11-25 15:06:36 +01:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
N. Engelhardt d67989f9ad update opt_muxtree iteration limit 2022-11-11 14:53:32 +01:00
Carlo Alberto Ferraris b5251b4802
Update opt_muxtree.cc 2022-11-06 21:59:40 +09:00
Carlo Alberto Ferraris 551d36d384
opt_muxtree: set iterations limit based on number of muxes 2022-11-03 21:18:21 +09:00
3 changed files with 30 additions and 7 deletions
Show Stats Expand all files Collapse all files

7
frontends/verific/verific.cc
View File

@ -2126,12 +2126,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log(" assert condition %s.\n", log_signal(cond));
Cell *cell = module->addAssert(new_verific_id(inst), cond, State::S1);
// Initialize FF feeding condition to 1, in case it is not
// used by rest of design logic, to prevent failing on
// initial uninitialized state
if (cond.is_wire() && !cond.wire->name.isPublic())
cond.wire->attributes[ID::init] = Const(1,1);
import_attributes(cell->attributes, inst);
continue;
}
@ -3428,6 +3422,7 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("veri_preserve_assignments", 1);
RuntimeFlags::SetVar("veri_preserve_comments", 1);
RuntimeFlags::SetVar("veri_preserve_drivers", 1);
RuntimeFlags::SetVar("veri_create_empty_box", 1);
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

6
passes/opt/opt_muxtree.cc
View File

@ -36,7 +36,7 @@ struct OptMuxtreeWorker
RTLIL::Module *module;
SigMap assign_map;
int removed_count;
int glob_abort_cnt = 100000;
int glob_abort_cnt;
struct bitinfo_t {
bool seen_non_mux;
@ -147,6 +147,10 @@ struct OptMuxtreeWorker
return;
}
// Limit the number of iterations based on the number of muxes.
// The multiplier (1000) is arbitrary.
glob_abort_cnt = max(100000, GetSize(mux2info) * 100);
// Populate mux2info[].ports[]:
// .input_muxes
for (int i = 0; i < GetSize(bit2info); i++)

24
tests/verific/blackbox.ys Normal file
View File

@ -0,0 +1,24 @@
verific -sv -lib <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
always @(posedge clk) begin
if (PATH=="DEFAULT")
c <= a;
else
c <= b;
end
endmodule
EOF
verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF
verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL