Clifford Wolf
931d775b0b
Merge pull request #322 from azonenberg/master
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Add POUT to GP_COUNTx cells
2017-02-24 19:23:29 +01:00
Clifford Wolf
7af9727f78
Add "write_smt2 -stbv"
2017-02-24 18:24:53 +01:00
Andrew Zonenberg
1f824fa643
Merge https://github.com/cliffordwolf/yosys
2017-02-24 08:12:45 -08:00
Clifford Wolf
a9c3acf5a2
Add SMT2 statebv mode (inactive for now)
2017-02-24 14:04:52 +01:00
Johann Klammer
6d7a77dbf6
Did as you requested, /but/...
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Now the nets are wired in reverse again because the netlister still uses zero-based indices.
2017-02-24 13:18:49 +01:00
Clifford Wolf
f648b7cf79
Merge pull request #320 from joshhead/uninstall-binpath-fix
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Add missing slashes in paths for make uninstall
2017-02-24 12:48:12 +01:00
Josh Headapohl
fde9fdfbe8
Add missing slashes in paths for make uninstall
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Running make uninstall used to fail to remove binaries:
rm -vf /usr/local/binyosys /usr/local/binyosys-config #...etc
Fix Makefile so that it runs a command like this:
rm -vf /usr/local/bin/yosys /usr/local/bin/yosys-config #...etc
2017-02-23 20:21:03 -05:00
Johann Klammer
06df86aae3
add options for edif flavors
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*to force renames on wide ports
*to choose array delimiters
*to choose up or downwards indices
2017-02-23 19:42:37 +01:00
Clifford Wolf
00dba4c197
Add support for SystemVerilog unique, unique0, and priority case
2017-02-23 16:33:19 +01:00
Clifford Wolf
1e927a51d5
Preserve string parameters
2017-02-23 15:39:13 +01:00
Clifford Wolf
c6d8d70109
Fix mingw compile issue (2nd attempt)
2017-02-23 14:21:02 +01:00
Clifford Wolf
0822b21844
Fix mingw compile issue (maybe.. I can't test it)
2017-02-23 13:59:02 +01:00
Clifford Wolf
34d4e72132
Added SystemVerilog support for ++ and --
2017-02-23 11:21:33 +01:00
Clifford Wolf
d25b6a72ee
Update ABC to hg rev 8da4dc435b9f
2017-02-22 19:20:47 +01:00
Clifford Wolf
242c5f01de
Add "yosys-smtbmc -S <opt>"
2017-02-19 22:51:29 +01:00
Andrew Zonenberg
2eabe43efa
Merge https://github.com/cliffordwolf/yosys
2017-02-16 07:48:44 -08:00
Clifford Wolf
cf25dc9ce7
Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
Clifford Wolf
e6d56d23b5
Fix eval implementation of $_NOR_
2017-02-16 12:17:03 +01:00
Andrew Zonenberg
6fed2dc996
Merge https://github.com/cliffordwolf/yosys
2017-02-14 08:29:37 -08:00
Clifford Wolf
4fb8007171
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
Clifford Wolf
4e80ce97a8
Add warning about x/z bits left unconnected in EDIF output
2017-02-14 12:49:35 +01:00
Clifford Wolf
2a311c2c38
Fix double-call of log_pop() in synth_greenpak4
2017-02-14 11:57:54 +01:00
Clifford Wolf
f3a25d9d34
Merge pull request #313 from azidar/bugfix-assign-wmask
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More progress on Firrtl backend.
2017-02-14 11:49:14 +01:00
Adam Izraelevitz
794cec0016
More progress on Firrtl backend.
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Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
2017-02-13 11:17:53 -08:00
Clifford Wolf
69468d5a16
Do not fix port widths on any blackbox instances
2017-02-13 17:07:38 +01:00
Clifford Wolf
db7314bc02
Fix techmap for inout ports connected to inout ports
2017-02-13 16:55:25 +01:00
Clifford Wolf
76c4ee096b
Do not eagerly fix port widths on parameterized cells
2017-02-12 17:42:57 +01:00
Clifford Wolf
828303791b
Add "yosys -w" for suppressing warnings
2017-02-12 11:11:00 +01:00
Andrew Zonenberg
203b521a78
Merge https://github.com/cliffordwolf/yosys
2017-02-11 11:25:16 -08:00
Clifford Wolf
cdb6ceb8c6
Add support for verific mem initialization
2017-02-11 15:57:36 +01:00
Clifford Wolf
c449f4b86f
Fix another stupid bug in the same line
2017-02-11 11:47:51 +01:00
Clifford Wolf
fa4a7efe15
Add verific support for initialized variables
2017-02-11 11:40:18 +01:00
Clifford Wolf
0b7aac645c
Improve handling of Verific warnings and error messages
2017-02-11 11:39:50 +01:00
Clifford Wolf
eb7b18e897
Fix extremely stupid typo
2017-02-11 11:09:07 +01:00
Clifford Wolf
63dfdb5d7f
Add log_wire() API
2017-02-11 11:08:36 +01:00
Clifford Wolf
95dae6d416
Fixed some "used uninitialized" warnings in opt_expr
2017-02-11 10:50:48 +01:00
Clifford Wolf
6d4e8673cc
Evaluate all the $(shell ...) stuff for CXXFLAGS et al only once
2017-02-11 10:28:13 +01:00
Clifford Wolf
a431f4ee31
Merge branch 'stv0g-master'
2017-02-11 10:20:10 +01:00
Clifford Wolf
a1a82d68f5
Make MacOS Makefile stuff more compact
2017-02-11 10:19:21 +01:00
Clifford Wolf
a88e019b0c
Merge branch 'master' of https://github.com/stv0g/yosys into stv0g-master
2017-02-11 10:12:17 +01:00
Clifford Wolf
a5bfeb9e07
Add optimization of (a && 1'b1) and (a || 1'b0)
2017-02-11 10:05:00 +01:00
Clifford Wolf
9c1a7be636
Merge pull request #308 from C-Elegans/opt_compare_fix_pr
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Fix issue #306 , "Bug in opt -full"
2017-02-11 10:04:48 +01:00
C-Elegans
94b272077d
Fix issue #306 , "Bug in opt -full"
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Add check for whether the high bit in the constant expression is greater
than the width of the variable, and optimizes that to a constant 1 or
0
2017-02-10 10:38:02 -05:00
Steffen Vogel
422ffd5c06
Use pkg-config for linking tcl-tk
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Both MacPorts and Homebrew have a pkg-config file for TCL. So lets use it.
2017-02-10 10:06:54 -03:00
Steffen Vogel
9eca3671ab
Dont mix Homebrew and MacPorts build options
2017-02-10 10:04:42 -03:00
Steffen Vogel
a3f19f047c
Remove space after backslash
2017-02-09 19:08:21 -03:00
Steffen Vogel
94c76f85da
Applied fixes from @joshhead (thanks for your effors!)
2017-02-09 18:53:37 -03:00
Clifford Wolf
e6cc67b46f
Fix handling of init attributes with strange width
2017-02-09 16:06:58 +01:00
Clifford Wolf
848062088c
Add checker support to verilog front-end
2017-02-09 13:51:44 +01:00
Clifford Wolf
2ca8d483dd
Add "rand" and "rand const" verific support
2017-02-09 12:53:46 +01:00