Eddie Hung
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8bf45f34c4
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Remove dump call
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2019-08-07 21:36:02 -07:00 |
Eddie Hung
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2b6cdfb39f
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Move tests/various/opt* into tests/opt/
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2019-08-07 21:35:48 -07:00 |
Eddie Hung
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d5e8c0e6d3
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Remove ice40_unlut call, simply do equiv_opt on synth_ice40
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2019-08-07 21:33:56 -07:00 |
Eddie Hung
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35bf509603
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Add testcase from removed opt_ff.{v,ys}
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2019-08-07 21:31:32 -07:00 |
Eddie Hung
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4545bf482f
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Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run
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2019-08-07 16:48:38 -07:00 |
Eddie Hung
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9776084eda
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Allow whitebox modules to be overwritten
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2019-08-07 16:40:24 -07:00 |
Eddie Hung
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9962e6fc1a
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Update CHANGELOG
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2019-08-07 16:33:46 -07:00 |
Eddie Hung
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675c1d4218
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Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
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2019-08-07 16:29:38 -07:00 |
Eddie Hung
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cc331cf70d
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Add test
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2019-08-07 16:29:38 -07:00 |
Eddie Hung
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ea8ac8fd74
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Remove ice40_unlut
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2019-08-07 16:29:38 -07:00 |
Eddie Hung
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6b314c8371
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Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
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2019-08-07 16:29:38 -07:00 |
Eddie Hung
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f69410daaf
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opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
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2019-08-07 13:15:02 -07:00 |
Eddie Hung
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3414ee1e3f
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Merge pull request #1248 from YosysHQ/eddie/abc9_speedup
abc9: speedup by using using "clean" more efficiently
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2019-08-07 12:25:26 -07:00 |
Eddie Hung
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6d77236f38
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substr() -> compare()
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2019-08-07 12:20:08 -07:00 |
Eddie Hung
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71eff6f0de
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RTLIL::S{0,1} -> State::S{0,1} for headers
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2019-08-07 11:14:03 -07:00 |
Eddie Hung
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7164996921
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07 11:12:38 -07:00 |
Eddie Hung
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e6d5147214
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Merge remote-tracking branch 'origin/master' into eddie/cleanup
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2019-08-07 11:11:50 -07:00 |
Eddie Hung
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0c78c62d6c
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Remove std:: namespace
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2019-08-07 11:11:14 -07:00 |
Eddie Hung
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13b7d2252e
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'make clean' to not remove anything abc
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2019-08-07 11:10:18 -07:00 |
Eddie Hung
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48d0f99406
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stoi -> atoi
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2019-08-07 11:09:17 -07:00 |
1138-4EB
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36c80cf456
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dockerfile: use 'python:3-slim-buster' base image
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2019-08-07 20:07:45 +02:00 |
1138-4EB
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99de39fc79
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dockerfile: use PREFIX instead of cp
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2019-08-07 20:07:45 +02:00 |
Jim Lawson
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5e8a98c8fd
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Merge branch 'master' into firrtl_err_on_unsupported_cell
# Conflicts:
# backends/firrtl/firrtl.cc
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2019-08-07 10:14:45 -07:00 |
Eddie Hung
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58e512ab70
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Add comment
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2019-08-07 09:54:27 -07:00 |
Eddie Hung
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f20acbc813
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Revert "Add TODO"
This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
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2019-08-07 09:54:27 -07:00 |
Eddie Hung
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789585a744
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Add TODO
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2019-08-07 09:54:27 -07:00 |
Eddie Hung
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8a8c1d7857
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Compute box_lookup just once
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2019-08-07 09:54:27 -07:00 |
Eddie Hung
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03ec8d6551
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Run "clean" on mapped_mod in its own design
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2019-08-07 09:54:27 -07:00 |
Eddie Hung
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3090da2d98
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Run "clean -purge" on holes_module in its own design
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2019-08-07 09:54:27 -07:00 |
David Shah
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5545cd3c10
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Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
ecp5: Make cells_sim.v consistent with nextpnr
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2019-08-07 15:35:29 +01:00 |
Clifford Wolf
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9260e97aa2
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Automatically prune init attributes in verific front-end, fixes #1237
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-07 15:31:49 +02:00 |
David Shah
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a36fd8582e
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ecp5: Make cells_sim.v consistent with nextpnr
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-07 14:19:31 +01:00 |
Clifford Wolf
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e9a756aa7a
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Merge pull request #1213 from YosysHQ/eddie/wreduce_add
wreduce/opt_expr: improve width reduction for $add and $sub cells
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2019-08-07 14:27:35 +02:00 |
Clifford Wolf
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48f7682e32
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Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
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2019-08-07 12:31:32 +02:00 |
Clifford Wolf
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4c49ddf36a
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Merge pull request #1249 from mmicko/anlogic_fix
anlogic : Fix alu mapping
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2019-08-07 12:30:52 +02:00 |
Clifford Wolf
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679bc6507f
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Merge pull request #1252 from YosysHQ/clifford/fix1231
Fix handling of functions/tasks without top-level begin-end block
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2019-08-07 12:14:54 +02:00 |
Clifford Wolf
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c5d56fbe2d
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Merge pull request #1253 from YosysHQ/clifford/check
Be less aggressive with running design->check()
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2019-08-07 12:14:41 +02:00 |
Clifford Wolf
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f1ac998bb4
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Merge pull request #1257 from YosysHQ/clifford/cellcosts
Redesign of cell cost API
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2019-08-07 12:13:50 +02:00 |
David Shah
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607c7fa7e1
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Update CHANGELOG
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-07 10:56:32 +01:00 |
David Shah
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dee8f61781
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Merge pull request #1241 from YosysHQ/clifford/jsonfix
Improved JSON attr/param encoding
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2019-08-07 10:40:38 +01:00 |
Clifford Wolf
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338f6765eb
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Tweak default gate costs, cleanup "stat -tech cmos"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-07 10:25:51 +02:00 |
Bogdan Vukobratovic
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067b44938c
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Fix wrong results when opt_share called before opt_clean
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2019-08-07 09:30:58 +02:00 |
1138-4EB
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5e2919de02
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dockerfile: add ARG IMAGE, use three stages
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2019-08-07 05:38:09 +02:00 |
1138-4EB
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3463511601
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dockerfile: reduce number of COPY layers
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2019-08-07 05:38:01 +02:00 |
1138-4EB
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1f801993e3
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dockerfile: DEBIAN_FRONTEND should not be permanent
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2019-08-07 05:37:52 +02:00 |
Eddie Hung
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ee7c970367
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IdString::str().substr() -> IdString::substr()
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2019-08-06 19:08:33 -07:00 |
Eddie Hung
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234fcf1724
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Fix typos
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2019-08-06 19:07:45 -07:00 |
Eddie Hung
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e5be9ff871
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Fix spacing
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2019-08-06 16:47:55 -07:00 |
Eddie Hung
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c11ad24fd7
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Use std::stoi instead of atoi(<str>.c_str())
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2019-08-06 16:45:48 -07:00 |
Eddie Hung
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e38f40af5b
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Use IdString::begins_with()
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2019-08-06 16:42:25 -07:00 |