yosys

Commit Graph

Author	SHA1	Message	Date
Zachary Snow	4b2f977331	genrtlil: fix signed port connection codegen failures This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.	2021-02-05 19:51:30 -05:00
Zachary Snow	0d8e5d965f	Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265	2020-12-18 20:33:14 -07:00

Author

SHA1

Message

Date

Zachary Snow

4b2f977331

genrtlil: fix signed port connection codegen failures

This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.

2021-02-05 19:51:30 -05:00

Zachary Snow

0d8e5d965f

Sign extend port connections where necessary

- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265

2020-12-18 20:33:14 -07:00

2 Commits