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yosys
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2,348 Commits 81 Branches 48 Tags 63 MiB
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2348 Commits

Author SHA1 Message Date
Clifford Wolf 4d34d031f9 Added "stat" to "synth" and "synth_xilinx" 2015-02-15 13:25:15 +01:00
Clifford Wolf 881dcd8af9 Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
Clifford Wolf 40f021e136 Added "check -noinit" 2015-02-15 12:58:12 +01:00
Clifford Wolf a54c994e2b Cosmetic fixes in "hierarchy" for blackbox modules 2015-02-15 12:57:41 +01:00
Clifford Wolf 3216f9420e More emscripten stuff, Added example app 2015-02-15 12:09:30 +01:00
Clifford Wolf 86819cc9f8 Fixed default EMCCFLAGS 2015-02-15 10:30:29 +01:00
Clifford Wolf ec05242c27 Smaller default parameters in $mem simlib model 2015-02-15 00:20:05 +01:00
Clifford Wolf c6ae9ebb79 Fixed "stat" handling of blackbox modules 2015-02-14 22:36:34 +01:00
Clifford Wolf e9368a1d7e Various fixes for memories with offsets 2015-02-14 14:21:15 +01:00
Clifford Wolf dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf 913c304fe6 Added $meminit test case 2015-02-14 11:26:20 +01:00
Clifford Wolf 7f1a1759d7 Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
Clifford Wolf a8e9d37c14 Creating $meminit cells in verilog front-end 2015-02-14 10:49:30 +01:00
Clifford Wolf 910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf ef151b0b30 Fixed handling of "//" in filenames in verilog pre-processor 2015-02-14 08:41:03 +01:00
Clifford Wolf 756b4064b2 Fixed "write_verilog -attr2comment" handling of "*/" in strings 2015-02-13 22:48:10 +01:00
Clifford Wolf a0a0594d1e hotfix in "check" command 2015-02-13 14:40:49 +01:00
Clifford Wolf 04cb947d6a Added "check" command 2015-02-13 14:34:51 +01:00
Clifford Wolf cd919abdf1 Added AstNode::simplify() recursion counter 2015-02-13 12:33:12 +01:00
Clifford Wolf 2f0edff019 Added EMCCFLAGS 2015-02-13 12:32:04 +01:00
Clifford Wolf d58c3eca3a Some test related fixes 
(incl. removal of three bad test cases)
 2015-02-12 17:45:44 +01:00
Clifford Wolf 554a8df5e2 Added "proc_dlatch" 2015-02-12 16:56:01 +01:00
Clifford Wolf 87819c62fa Less aggressive "share" defaults 2015-02-10 20:51:37 +01:00
Clifford Wolf 4f68a77e3f Improved read_verilog support for empty behavioral statements 2015-02-10 12:17:29 +01:00
Clifford Wolf 510deb3577 Added "scc -expect <N> -nofeedback" 2015-02-10 08:48:55 +01:00
Clifford Wolf adf4ecbc1f Some hashlib improvements 2015-02-09 20:11:51 +01:00
Clifford Wolf 68979d1395 Various changes to release checklist 2015-02-09 16:36:37 +01:00
Clifford Wolf a779a09771 Fixed creation of command reference in manual 2015-02-09 13:24:29 +01:00
Clifford Wolf e0ff4d1152 We are now in 0.5+ development 2015-02-09 13:13:51 +01:00
Clifford Wolf c3c9fbfb8c Yosys 0.5 2015-02-09 12:49:52 +01:00
Clifford Wolf 8901f405ca Bugfix in "make vcxsrc" 2015-02-09 12:48:15 +01:00
Clifford Wolf b944fef925 Updated command reference in manual 2015-02-09 12:05:02 +01:00
Clifford Wolf 85887de547 Various presentation fixes 2015-02-09 12:02:21 +01:00
Clifford Wolf f889e3d385 Fixed iterator invalidation bug in "rename" command 2015-02-09 00:18:36 +01:00
Clifford Wolf 139648554d CodingReadme update 2015-02-08 23:30:15 +01:00
Clifford Wolf 07afb14318 Fixed bug in "show -format .." 2015-02-08 23:29:54 +01:00
Clifford Wolf 183d4f8e71 Added new APIs to changelog 2015-02-08 21:14:52 +01:00
Clifford Wolf bcd8a2fc56 Fixed eval_select_op() api 2015-02-08 19:06:16 +01:00
Clifford Wolf 09ee65a050 Added eval_select_args() and eval_select_op() 2015-02-08 18:56:06 +01:00
Clifford Wolf 0fcc8c1467 Minor "make vgtest" changes 2015-02-08 15:13:51 +01:00
Clifford Wolf 6d2f31c04a Various ModIndex improvements 2015-02-08 14:23:12 +01:00
Clifford Wolf b10f0088d1 Added Yosys 0.5 Changelog 2015-02-08 12:03:51 +01:00
Clifford Wolf c3ce824af0 Various updates to CodingReadme 2015-02-08 12:03:51 +01:00
Clifford Wolf 5170b86108 Added equiv_add 2015-02-08 11:59:38 +01:00
Clifford Wolf 234a45a3d5 Ignore explicit assignments to constants in HDL code 2015-02-08 00:58:03 +01:00
Clifford Wolf c8305e3a6d Fixed a bug with autowire bit size 
(removed leftover from when we tried to auto-size the wires)
 2015-02-08 00:48:23 +01:00
Clifford Wolf fbb16712f1 fixed typo 2015-02-08 00:16:59 +01:00
Clifford Wolf bbfc1bd7cf Added "yosys-config --build modname.so cppsources.." 2015-02-08 00:14:07 +01:00
Clifford Wolf 05d4223fb6 Added SigSpec::has_const() 2015-02-08 00:01:51 +01:00
Clifford Wolf 0da320f151 Cleanup in add_share_file make macro 2015-02-08 00:01:31 +01:00