8 Commits

Author	SHA1	Message	Date
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	08ceb3729e	Fixed ilang parser: memory width	2013-11-20 19:55:52 +01:00
Clifford Wolf	77726fb5fe	Fixed parsing of value-less attributes in ilang	2013-10-23 18:38:31 +02:00
Clifford Wolf	375f83c5ec	Fixed memory leak in ilang frontend	2013-05-23 12:55:59 +02:00
Clifford Wolf	8a6b0a3520	Added help messages to ilang and verilog frontends	2013-03-01 08:03:00 +01:00
Clifford Wolf	6543917fb8	added .gitignore files	2013-01-05 11:19:11 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00