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yosys
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2669 Commits

Author SHA1 Message Date
Clifford Wolf 0fbc1a59dd Progress in presentation 2014-02-17 09:45:04 +01:00
Clifford Wolf ca53ef5098 Better preserve wires when flattening (in comparison to techmap) 2014-02-17 09:44:39 +01:00
Clifford Wolf 37cbb1ca60 Progress in presentation 2014-02-16 22:31:53 +01:00
Clifford Wolf 6d63f39eb6 Added some additional checks to techmap 2014-02-16 22:18:06 +01:00
Clifford Wolf a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap 2014-02-16 21:58:59 +01:00
Clifford Wolf 28e14ee50a Fixed handling of "keep" attribute on wires in opt_clean 2014-02-16 21:58:27 +01:00
Clifford Wolf 7d7e068dd1 Added a warning note about error reporting to read_verilog help message 2014-02-16 20:20:25 +01:00
Clifford Wolf f08c71b96c Progress in presentation 2014-02-16 17:56:19 +01:00
Clifford Wolf 42ce3db983 Fixed use of selection in splitnets command 2014-02-16 17:39:50 +01:00
Clifford Wolf d3dc22a90f Added recursion support to techmap 2014-02-16 17:16:44 +01:00
Clifford Wolf aeb36b0b8b Progress in presentation 2014-02-16 14:32:56 +01:00
Clifford Wolf 9c29969bbc Progress in presentation 2014-02-16 13:45:47 +01:00
Clifford Wolf 7ac524e8e8 Improved support for constant functions 2014-02-16 13:16:38 +01:00
Clifford Wolf b0ae19fa92 Now we are in Yoys 0.2.0+ development 2014-02-16 00:54:41 +01:00
Clifford Wolf c05c3098f1 Tagging Yoys 0.2.0 2014-02-16 00:35:53 +01:00
Clifford Wolf 9a816b65a8 Added != support for relational select pattern 2014-02-16 00:16:54 +01:00
Clifford Wolf 623a68f528 Added iopadmap -bits 2014-02-15 21:59:26 +01:00
Clifford Wolf 118517ca5a Added ff and latch support to read_liberty 2014-02-15 19:44:19 +01:00
Clifford Wolf 96b1ebc8dc Bugfix in expression parser of read_liberty 2014-02-15 19:36:09 +01:00
Clifford Wolf cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff 2014-02-15 16:34:12 +01:00
Clifford Wolf 5e39e6ece2 Correctly convert constants to RTLIL (fixed undef handling) 2014-02-15 15:42:10 +01:00
Clifford Wolf 30379ea20d Added frontend (-f) option to autotest.sh 2014-02-15 15:40:17 +01:00
Clifford Wolf 67effc9f5b Fixed opt_const handling of double invert with non-1 output width 2014-02-15 13:16:08 +01:00
Clifford Wolf 4440610d3f Added liberty frontend 2014-02-15 12:57:28 +01:00
Clifford Wolf 45d2b6ffce Be more conservative with new const-function code 2014-02-14 20:45:30 +01:00
Clifford Wolf e8af3def7f Added support for FOR loops in function calls in parameters 2014-02-14 20:33:22 +01:00
Clifford Wolf 534c1a5dd0 Created basic support for function calls in parameter values 2014-02-14 19:56:44 +01:00
Clifford Wolf 3121d19d95 Added abc -keepff option 2014-02-14 11:28:42 +01:00
Clifford Wolf de3ea9269a updated default ABC command strings 2014-02-13 19:14:15 +01:00
Clifford Wolf a123941618 Updated ABC 2014-02-13 18:56:36 +01:00
Clifford Wolf cd9e8741a7 Implemented read_verilog -defer 2014-02-13 13:59:13 +01:00
Clifford Wolf b463907890 Removed double blanks in ABC default command sequences 2014-02-13 08:12:52 +01:00
Clifford Wolf c6236c9e97 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-13 08:09:17 +01:00
Clifford Wolf 7664f5d92b Updated ABC and some related changes 2014-02-13 08:07:08 +01:00
Clifford Wolf 6b210d2b6f Merge pull request #26 from ahmedirfan1983/btor 
Btor
 2014-02-12 23:46:58 +01:00
Clifford Wolf 08caa631dd Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-12 23:30:02 +01:00
Clifford Wolf 007bdff55d Added support for functions returning integer 2014-02-12 23:29:54 +01:00
Ahmed Irfan ac896c63e2 modified btor synthesis script for correct use of splice command. 2014-02-12 13:38:28 +01:00
Clifford Wolf 9ce7b0fc3b Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC) 2014-02-12 13:11:58 +01:00
Clifford Wolf ab71bd0746 Updated ABC to rev e97a6e1d59b9 2014-02-12 08:35:42 +01:00
Clifford Wolf 0defc86519 renamed ilang "scope error" to "ilang error" 2014-02-11 19:17:07 +01:00
Ahmed Irfan 45e468114a disabling splice command in the script 2014-02-11 15:43:03 +01:00
Ahmed Irfan 1d64b3e008 register output corrected 2014-02-11 13:28:05 +01:00
Ahmed Irfan 1a2dc48c2a Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 2014-02-11 13:26:43 +01:00
Ahmed Irfan e8f6b8f201 added concat and slice cell translation 2014-02-11 13:06:01 +01:00
Clifford Wolf d2fd45949d More Makefile cleanups 2014-02-11 12:58:08 +01:00
Clifford Wolf 4bd2d47e45 Improved "make manual" and "make clean" 2014-02-11 12:55:58 +01:00
Clifford Wolf fb186e6299 Improved ilang parser error messages 2014-02-09 15:35:31 +01:00
Clifford Wolf d229324420 fixed a bug in subcircuit library with cells that have connections to itself 2014-02-09 15:27:58 +01:00
Clifford Wolf 38469e7686 Various improvements in expose command (added -sep and -cut) 2014-02-09 11:07:46 +01:00