5 Commits

Author	SHA1	Message	Date
Dan Ravensloft	67b4ce06e0	intel: Map M9K BRAM only on families that have it ... This regresses Cyclone V and Cyclone 10 substantially, but these numbers were artificial, targeting a BRAM that they did not contain. Amusingly, synth_intel still does better when synthesizing PicoSoC than Quartus when neither are inferring block RAM.	2019-07-23 18:11:11 +01:00
Diego H	819ca73096	Changes in GoWin synth commands and ALU primitive support	2018-12-03 20:08:35 -06:00
Larry Doolittle	50bcd9a728	Clean whitespace and permissions in techlibs/intel	2017-10-05 16:23:49 +02:00
dh73	4718e65763	Tested and working altsyncarm without init files	2017-10-01 19:59:45 -05:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00