Clifford Wolf
4f81213165
Merge pull request #1261 from YosysHQ/clifford/verific_init
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Automatically prune init attributes in verific front-end
2019-08-10 09:47:25 +02:00
Eddie Hung
446dcb3ed3
Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithro
2019-08-09 09:17:35 -07:00
Eddie Hung
9776084eda
Allow whitebox modules to be overwritten
2019-08-07 16:40:24 -07:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Eddie Hung
03ec8d6551
Run "clean" on mapped_mod in its own design
2019-08-07 09:54:27 -07:00
Clifford Wolf
9260e97aa2
Automatically prune init attributes in verific front-end, fixes #1237
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 15:31:49 +02:00
Clifford Wolf
679bc6507f
Merge pull request #1252 from YosysHQ/clifford/fix1231
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Fix handling of functions/tasks without top-level begin-end block
2019-08-07 12:14:54 +02:00
David Shah
dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix
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Improved JSON attr/param encoding
2019-08-07 10:40:38 +01:00
Eddie Hung
ee7c970367
IdString::str().substr() -> IdString::substr()
2019-08-06 19:08:33 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
a6bc9265fb
RTLIL::S{0,1} -> State::S{0,1}
2019-08-06 16:23:37 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Clifford Wolf
f1f5b4e375
Fix handling of functions/tasks without top-level begin-end block, fixes #1231
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 18:06:14 +02:00
Clifford Wolf
f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix
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Fix formatting for msys2 mingw build
2019-08-02 16:37:57 +02:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Clifford Wolf
292f03355a
Update JSON front-end to process new attr/param encoding
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-01 12:48:22 +02:00
Clifford Wolf
acd8bc0a74
Merge pull request #1233 from YosysHQ/clifford/defer
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Call "read_verilog" with -defer from "read"
2019-07-31 13:30:52 +02:00
Clifford Wolf
fc462c8243
Call "read_verilog" with -defer from "read"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-29 10:29:36 +02:00
David Shah
92694ea3a9
verilog_lexer: Increase YY_BUF_SIZE to 65536
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 13:35:39 +01:00
Jakob Wenzel
e2fe8e0a4f
initialize noblackbox and nowb in AstModule::clone
2019-07-22 10:37:40 +02:00
Miodrag Milanovic
6cce679b35
Fix typo, double "of"
2019-07-16 11:03:30 +02:00
William D. Jones
da5d64d71e
Fix missing semicolon in Windows-specific code in aigerparse.cc.
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Signed-off-by: William D. Jones <thor0505@comcast.net>
2019-07-14 13:52:27 -04:00
Eddie Hung
a314565ad4
Short out async box
2019-07-11 10:52:45 -07:00
Eddie Hung
bd198aa803
Missing debug message
2019-07-11 10:07:14 -07:00
Eddie Hung
f8f0ffe786
Small opt
2019-07-10 18:56:50 -07:00
Eddie Hung
4a995c5d80
Change how to specify flops to ABC again
2019-07-10 17:54:56 -07:00
Eddie Hung
a092c48f03
Use split_tokens()
2019-07-10 17:34:51 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
whitequark
b1f400aeb8
genrtlil: emit \src attribute on CaseRule.
2019-07-08 12:29:08 +00:00
whitequark
93bc5affd3
Allow attributes on individual switch cases in RTLIL.
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The parser changes are slightly awkward. Consider the following IL:
process $0
<point 1>
switch \foo
<point 2>
case 1'1
assign \bar \baz
<point 3>
...
case
end
end
Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.
To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.
Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
Clifford Wolf
e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144
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Improve specify dummy parser
2019-07-03 12:30:37 +02:00
Clifford Wolf
ba36567908
Some cleanups in "ignore specify parser"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:22:10 +02:00
Eddie Hung
35fd9b0473
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-02 12:35:45 -07:00
Clifford Wolf
d206eca03b
Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-02 11:36:26 +02:00
Eddie Hung
a31e17182d
Refactor and cope with new abc_flop format
2019-07-01 11:50:34 -07:00
Eddie Hung
ac5f3d500d
Fix spacing
2019-07-01 11:10:44 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Eddie Hung
b3f162e94e
Replace log_assert() with meaningful log_error()
2019-06-28 12:54:44 -07:00
Clifford Wolf
af74409749
Improve specify dummy parser, fixes #1144
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-28 10:21:16 +02:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
469f98b6bd
Remove unneeded include
2019-06-27 11:20:40 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Clifford Wolf
f6053b8810
Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 11:09:43 +02:00
Eddie Hung
cec2292b0b
Merge remote-tracking branch 'origin/master' into xaig
2019-06-24 20:01:43 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
f2ead4334a
Reduce log_debug spam in parse_xaiger()
2019-06-21 17:33:49 -07:00
Eddie Hung
b75863ca3f
Workaround issues exposed by gcc-4.8
2019-06-21 14:31:09 -07:00
Miodrag Milanovic
50e7221077
Add upto and offset to JSON ports
2019-06-21 19:47:25 +02:00
Miodrag Milanovic
3775763f51
Fix typo
2019-06-21 19:09:34 +02:00
Clifford Wolf
f15def325c
Added JSON upto and offset
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 15:22:17 +02:00
Clifford Wolf
78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118
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Make genvar a signed type
2019-06-21 10:13:13 +02:00
Eddie Hung
9faeba7a66
Fix broken abc9.v test due to inout being 1'bx
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
014606affe
Fix issue with part of PI being 1'bx
2019-06-20 17:38:16 -07:00
Eddie Hung
c27ab609fa
Make genvar a signed type
2019-06-20 16:04:12 -07:00
Eddie Hung
20119ee50e
Maintain "is_unsized" state of constants
2019-06-20 12:43:39 -07:00
Clifford Wolf
2428fb7dc2
Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays
2019-06-20 12:03:00 +02:00
Clifford Wolf
ec4565009a
Add "read_verilog -pwires" feature, closes #1106
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 14:38:50 +02:00
Tobias Wölfel
8b8af10f5e
Unpacked array declaration using size
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Allows fixed-sized array dimension specified by a single number.
This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560 .
But is split out of the original work.
2019-06-19 12:47:48 +02:00
Clifford Wolf
8d0cd529c9
Add defaultvalue attribute
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:37:11 +02:00
Clifford Wolf
6d64e242ba
Fix handling of "logic" variables with initial value
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:25:11 +02:00
Eddie Hung
0c59bc0b75
Cleanup
2019-06-16 10:42:00 -07:00
Eddie Hung
fb90d8c18c
Cleanup
2019-06-16 09:34:26 -07:00
Eddie Hung
3d1185b835
Read init from outputs
2019-06-15 22:41:42 -07:00
Eddie Hung
c04921c3a8
Fix debug message
2019-06-15 18:13:44 -07:00
Eddie Hung
b706ae82de
Fix log_debug messages
2019-06-15 12:42:18 -07:00
Eddie Hung
7a3c403ba0
Missing close bracket
2019-06-15 09:10:01 -07:00
Eddie Hung
2ef2aa997c
read_aiger to not require clk_name for latches, plus debug
2019-06-15 09:07:53 -07:00
Eddie Hung
7876b5b8be
Cover __APPLE__ too for little to big endian
2019-06-14 12:40:51 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Eddie Hung
97d2656375
Resolve comments from @daveshah1
2019-06-14 12:00:02 -07:00
Eddie Hung
a3be25ab0d
Cleanup
2019-06-14 10:27:30 -07:00
Eddie Hung
d005568f2e
Add TODO to parse_xaiger
2019-06-14 10:11:13 -07:00
Eddie Hung
bc22e2e3ee
Optimise some more
2019-06-13 17:02:58 -07:00
Eddie Hung
d09d4e0706
Move ConstEvalAig to aigerparse.cc
2019-06-13 16:28:11 -07:00
Eddie Hung
d39a5a77a9
Add ConstEvalAig specialised for AIGs
2019-06-13 13:13:48 -07:00
Eddie Hung
342fc0a600
parse_xaiger to cope with inouts
2019-06-12 15:45:46 -07:00
Eddie Hung
b21d29598a
Consistency
2019-06-12 09:40:51 -07:00
Eddie Hung
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
Udi Finkelstein
4b56f6646d
Fixed brojen $error()/$info/$warning() on non-generate blocks
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(within always/initial blocks)
2019-06-11 02:52:06 +03:00
Eddie Hung
2b350401c4
Fix spacing from spaces to tabs
2019-06-07 15:44:57 -07:00
Eddie Hung
6934f4bdd5
Fix spacing (entire file is wrong anyway, will fix later)
2019-06-07 11:30:36 -07:00
Eddie Hung
d00ae1d6a8
Remove unnecessary std::getline() for ASCII
2019-06-07 11:28:25 -07:00
Eddie Hung
a04521c6b7
Fix read_aiger -- create zero driver, fix init width, parse 'b'
2019-06-07 11:07:15 -07:00
Clifford Wolf
211d85cfcc
Fixes and cleanups in AST_TECALL handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 12:41:09 +02:00
Clifford Wolf
a3bbc5365b
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
2019-06-07 12:08:42 +02:00
Clifford Wolf
a0b57f2a6f
Cleanup tux3-implicit_named_connection
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection
2019-06-07 11:41:54 +02:00
tux3
88f5977093
SystemVerilog support for implicit named port connections
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This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
2019-06-06 18:07:49 +02:00
Clifford Wolf
b894187cf6
Merge pull request #1060 from antmicro/parsing_attr_on_port_conn
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Added support for parsing attributes on port connections.
2019-06-06 12:34:05 +02:00
Maciej Kurc
03e0d3a17c
Fixed memory leak.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-05 10:42:43 +02:00
Clifford Wolf
36120fcc30
Only support Symbiotic EDA flavored Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-02 10:14:50 +02:00
Maciej Kurc
a6cadf6318
Added support for parsing attributes on port connections.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-31 14:58:43 +02:00
Clifford Wolf
2faa1d0e80
Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-30 10:04:26 +02:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor
2019-05-27 19:07:46 +02:00
Stefan Biereigel
cd12f2ddcf
remove leftovers from ast data structures
2019-05-27 18:01:44 +02:00
Stefan Biereigel
ed625a3102
move wand/wor resolution into hierarchy pass
2019-05-27 18:00:22 +02:00
Clifford Wolf
92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range
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Give error instead of asserting for invalid range, fixes #947
2019-05-27 13:26:12 +02:00
Miodrag Milanovic
84ffb21708
Give error instead of asserting for invalid range, fixes #947
2019-05-27 12:25:18 +02:00
Miodrag Milanovic
34417ce55f
Added support for unsized constants, fixes #1022
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Includes work from @sumit0190 and @AaronKel
2019-05-27 11:42:10 +02:00
Stefan Biereigel
85de9d26c1
fix assignment of non-wires
2019-05-23 17:55:56 +02:00
Stefan Biereigel
fd003e0e97
fix indentation across files
2019-05-23 13:57:27 +02:00
Stefan Biereigel
075a48d3fa
implementation for assignments working
2019-05-23 13:57:27 +02:00
Stefan Biereigel
9df04d7e75
make lexer/parser aware of wand/wor net types
2019-05-23 13:57:27 +02:00
Eddie Hung
7057753427
Rename label
2019-05-21 18:20:31 -07:00
Eddie Hung
b5a29460b9
Try again
2019-05-21 17:20:19 -07:00
Eddie Hung
1bff09f2ff
Fix warning
2019-05-21 16:26:20 -07:00
Kaj Tuomi
48ddbe52fb
Read bigger Verilog files.
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Hit parser limit with 3M gate design. This commit fix it.
2019-05-18 14:20:30 +03:00
Clifford Wolf
b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes
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Support for attributes on parameters and localparams for Verilog frontend
2019-05-16 14:21:18 +02:00
Maciej Kurc
ce4a0954bc
Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:44:16 +02:00
Henner Zeller
8eb2798776
Make the generated *.tab.hh include all the headers needed to define the union.
2019-05-14 21:07:26 -07:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
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Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf
1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
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Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf
7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
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Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf
d187be39d6
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
2019-05-06 15:41:13 +02:00
Clifford Wolf
20268d12a5
Fix the other bison warning in ilang_parser.y
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 15:38:43 +02:00
Clifford Wolf
1cd1b5fc1a
Add "real" keyword to ilang format
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:00:40 +02:00
Clifford Wolf
c7f2e93024
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
2019-05-06 11:46:10 +02:00
Ben Widawsky
a98069d762
verilog_parser: Fix Bison warning
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As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
%name-prefix "frontend_verilog_yy"
For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html
Compile tested only.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-05 19:36:27 -07:00
Clifford Wolf
70d0f389ad
Merge pull request #988 from YosysHQ/clifford/fix987
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Add approximate support for SV "var" keyword
2019-05-04 21:58:25 +02:00
Clifford Wolf
66d6ca2de2
Add support for SVA "final" keyword
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 09:25:32 +02:00
Clifford Wolf
87426f5a06
Improve write_verilog specify support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
Clifford Wolf
9804c86e87
Add approximate support for SV "var" keyword, fixes #987
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 07:52:51 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Eddie Hung
c7d7d8ad1b
For hier_tree::Elaborate() also include SV root modules (bind)
2019-05-03 20:53:25 +02:00
Eddie Hung
3ea54ec400
Fix verific_parameters construction, use attribute to mark top netlists
2019-05-03 20:53:25 +02:00
Eddie Hung
a27b42e975
WIP -chparam support for hierarchy when verific
2019-05-03 20:53:25 +02:00
Eddie Hung
0f1a4cc03c
verific_import() changes to avoid ElaborateAll()
2019-05-03 20:53:25 +02:00
Udi Finkelstein
ac10e7d96d
Initial implementation of elaboration system tasks
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(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
Clifford Wolf
6bbe2fdbf3
Add splitcmplxassign test case and silence splitcmplxassign warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
Clifford Wolf
3b6a02d3a7
Fix width detection of memory access with bit slice, fixes #974
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:57:26 +02:00
Clifford Wolf
59d74a3348
Re-enable "final loop assignment" feature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:02:39 +02:00
Clifford Wolf
e35fe1344d
Disabled "final loop assignment" feature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 20:22:50 +02:00
Clifford Wolf
9c7d23446d
Merge pull request #972 from YosysHQ/clifford/fix968
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Add final loop variable assignment when unrolling for-loops
2019-04-30 18:09:44 +02:00
Clifford Wolf
84f3a796e1
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:37:46 +02:00
Clifford Wolf
9af825e31e
Add final loop variable assignment when unrolling for-loops, fixes #968
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:03:32 +02:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Eddie Hung
d9c915042a
Move clean from aigerparse to abc9
2019-04-23 13:42:35 -07:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
012c6af088
Allow $specify[23] cells in blackbox modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
b232e027bf
Checking and fixing specify cells in genRTLIL
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
41b843c27b
Un-break default specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
3cc95fb4be
Add specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Eddie Hung
5f30a8795d
Tidy up
2019-04-22 17:47:05 -07:00
Eddie Hung
8f30019b68
Revert "Temporarily remove 'r' extension"
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This reverts commit eaf3c24772
.
2019-04-22 17:41:21 -07:00
Eddie Hung
eaf3c24772
Temporarily remove 'r' extension
2019-04-22 11:54:19 -07:00
Eddie Hung
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
Clifford Wolf
bc98a463a4
Merge pull request #952 from YosysHQ/clifford/fix370
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Determine correct signedness and expression width in for-loop unrolling
2019-04-22 20:10:46 +02:00
Clifford Wolf
4ad0ea5c3c
Determine correct signedness and expression width in for loop unrolling, fixes #370
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 18:19:02 +02:00
Clifford Wolf
e158ea2097
Add log_debug() framework
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
Clifford Wolf
b40af877f3
Merge pull request #909 from zachjs/master
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support repeat loops with constant repeat counts outside of constant functions
2019-04-22 08:51:34 +02:00
Eddie Hung
42a6e0b0b9
Merge remote-tracking branch 'origin/clifford/libwb' into xaig
2019-04-21 14:49:18 -07:00
Clifford Wolf
5b7fea5245
Add "noblackbox" attribute
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-21 11:40:09 +02:00
Clifford Wolf
fb7f02be55
New behavior for front-end handling of whiteboxes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 22:24:50 +02:00
Eddie Hung
21701cc1df
read_aiger to parse 'r' extension
2019-04-18 17:39:36 -07:00
Eddie Hung
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Eddie Hung
e1b550d203
Ignore a/i/o/h XAIGER extensions
2019-04-17 10:55:23 -07:00
Eddie Hung
fecafb2207
Forgot backslashes
2019-04-12 18:22:44 -07:00
Eddie Hung
9bfcd80063
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
2019-04-12 18:21:16 -07:00
Eddie Hung
c776db3320
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-04-12 17:09:24 -07:00
Eddie Hung
acf3f5694b
Fix inout handling for -map option
2019-04-12 17:02:24 -07:00
Eddie Hung
ada130b459
Also cope with duplicated CIs
2019-04-12 16:17:12 -07:00
Eddie Hung
1c6f0cffd9
Cope with an output having same name as an input (i.e. CO)
2019-04-12 12:27:07 -07:00
Eddie Hung
1a49cf29d8
parse_aiger() to rename all $lut cells after "clean"
2019-04-10 14:02:23 -07:00
Zachary Snow
5855024ccc
support repeat loops with constant repeat counts outside of constant functions
2019-04-09 12:28:32 -04:00
Eddie Hung
36efec01b8
Fix spacing
2019-04-08 16:37:22 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Clifford Wolf
dfb242c905
Add "read_ilang -lib"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-05 17:31:49 +02:00
Clifford Wolf
584d2030bf
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-29 16:32:44 +01:00
Clifford Wolf
7682629b79
Add "read -verific" and "read -noverific"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 14:03:35 +01:00
Clifford Wolf
c863796e9f
Fix "verific -extnets" for more complex situations
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:17:46 +01:00
Clifford Wolf
638be461c3
Fix mem2reg handling of memories with upto data ports, fixes #888
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:21:17 +01:00
Clifford Wolf
da42f10765
Improve "read_verilog -dump_vlog[12]" handling of upto ranges
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:20:16 +01:00
Clifford Wolf
9b0e7af6d7
Improve read_verilog debug output capabilities
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 20:52:29 +01:00
Eddie Hung
02e8dc7ad2
Merge https://github.com/YosysHQ/yosys into read_aiger
2019-03-19 08:52:31 -07:00
Eddie Hung
3e89cf68bd
Add author name
2019-03-19 08:52:06 -07:00
Zachary Snow
a5f4b83637
fix local name resolution in prefix constructs
2019-03-18 20:43:20 -04:00
Clifford Wolf
17caaa3fa8
Improve handling of "full_case" attributes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 17:51:21 +01:00
Clifford Wolf
d25a0c8ade
Improve handling of memories used in mem index expressions on LHS of an assignment
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:12:02 +01:00
Clifford Wolf
a4ddc569b4
Remove outdated "blocking assignment to memory" warning
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:10:55 +01:00
Clifford Wolf
ab5b50ae3c
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 20:09:47 +01:00
Clifford Wolf
b02d9c2634
Fix handling of cases that look like sva labels, fixes #862
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-10 16:27:18 -07:00
Clifford Wolf
cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels
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Add support for using SVA labels in yosys-smtbmc console output
2019-03-09 11:14:57 -08:00
Clifford Wolf
e7a34d342e
Also add support for labels on sva module items, fixes #699
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-08 22:55:09 -08:00
Eddie Hung
ee013fba54
Update help message for -chparam
2019-03-09 01:56:16 +00:00
Eddie Hung
2aa3903757
Add -chparam option to verific command
2019-03-09 01:54:01 +00:00
Eddie Hung
1dc060f32e
Fix spelling
2019-03-09 00:43:50 +00:00
Clifford Wolf
a330c68363
Fix handling of task output ports in clocked always blocks, fixes #857
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 22:44:37 -08:00
Clifford Wolf
22ff60850e
Add support for SVA labels in read_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 11:17:32 -08:00
Clifford Wolf
cda37830b0
Add hack for handling SVA labels via Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 10:52:44 -08:00
Clifford Wolf
52f80718a7
Merge pull request #848 from YosysHQ/clifford/fix763
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Fix error for wire decl in always block, fixes 763
2019-03-02 16:32:58 -08:00
Clifford Wolf
ae9286386d
Only run derive on blackbox modules when ports have dynamic size
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 12:36:46 -08:00
Clifford Wolf
3a51714451
Fix error for wire decl in always block, fixes #763
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 11:56:44 -08:00
Clifford Wolf
ce6695e22c
Fix $global_clock handling vs autowire
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 10:38:13 -08:00
Clifford Wolf
5d93dcce86
Fix $readmem[hb] for mem2reg memories, fixes #785
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 09:58:20 -08:00
Clifford Wolf
7cfae2c52f
Use mem2reg on memories that only have constant-index write ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 13:35:09 -08:00
Clifford Wolf
60e3c38054
Improve "read" error msg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 20:34:42 -08:00
Eddie Hung
f7c7003a19
Merge remote-tracking branch 'origin/master' into xaig
2019-02-26 13:16:03 -08:00
Eddie Hung
da076344cc
parse_xaiger() to really pass single and multi-bit inout tests
2019-02-26 12:04:45 -08:00
Eddie Hung
8f02c846f6
parse_xaiger() to cope with multi bit inouts
2019-02-26 11:37:34 -08:00
Eddie Hung
316232a7dd
parse_xaiger() to untransform $inout.out output ports
2019-02-25 18:40:23 -08:00
Eddie Hung
721f6a14fb
read_aiger to accept empty string for clk_name, passable only if no latches
2019-02-25 15:34:02 -08:00
Clifford Wolf
1816fe06af
Fix handling of defparam for when default_nettype is none
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 20:09:41 +01:00
Clifford Wolf
a516b4fb5a
Check if Verific was built with DB_PRESERVE_INITIAL_VALUE
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-24 19:51:30 +01:00
Eddie Hung
07036b8bf7
read_aiger to work with symbol table
2019-02-21 17:01:07 -08:00
Eddie Hung
085ed9f487
Add attribution
2019-02-21 14:40:13 -08:00
Eddie Hung
3307295488
Merge branch 'read_aiger' into xaig
2019-02-21 14:27:32 -08:00
Clifford Wolf
23148ffae1
Fixes related to handling of autowires and upto-ranges, fixes #814
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 18:40:11 +01:00
Clifford Wolf
974927adcf
Fix handling of expression width in $past, fixes #810
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:55:33 +01:00
Clifford Wolf
28fba903c5
Fix segfault in printing of some internal error messages
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-21 17:40:52 +01:00
Eddie Hung
9e299a0908
read_aiger to not do -purge for clean
2019-02-20 17:33:04 -08:00
Eddie Hung
32853b1f8d
lut/not/and suffix to be ${lut,not,and}
2019-02-20 16:30:30 -08:00
Eddie Hung
abc1c2672e
read_aiger to also rename 0 index lut when wideports
2019-02-20 16:17:22 -08:00
Eddie Hung
f9702a8abe
read_aiger: new naming fixes
2019-02-20 12:39:51 -08:00
Eddie Hung
83b66861e9
read_aiger to name wires with internal name, less likely to clash
2019-02-20 11:22:56 -08:00
Eddie Hung
7b026c4bc3
Same for ascii AIGERs too
2019-02-19 15:15:50 -08:00
Eddie Hung
d304882cba
read_aiger to cope with non-unique POs
2019-02-19 15:14:08 -08:00
Eddie Hung
e79df5e70e
read_aiger to create sane $lut names, and rename when renaming driving wire
2019-02-19 12:27:50 -08:00
Eddie Hung
0b1fc46ae3
Add comment
2019-02-19 10:24:55 -08:00
Eddie Hung
54f719f446
Get rid of boost dep, fix the FIXMEs for Win32?
2019-02-19 10:19:53 -08:00
Eddie Hung
843e7fc8a7
Fix for using POSIX basename
2019-02-19 09:02:37 -08:00
Eddie Hung
8e1dbfac3a
Missing OSX headers?
2019-02-17 20:59:53 -08:00
Eddie Hung
9268a271fb
read_aiger to ignore line after ands for ascii, not binary
2019-02-17 12:07:14 -08:00
Eddie Hung
03a533d102
Merge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 11:44:01 -08:00
Eddie Hung
82459c16c4
In read_xaiger, do not construct ConstEval for every LUT
2019-02-16 22:22:29 -08:00
Eddie Hung
f60cd4ff9b
read_aiger to ignore output = input of same wire; also create new output for different wire
2019-02-16 21:53:03 -08:00
Eddie Hung
1a25ec4baa
read_aiger to disable log_debug
2019-02-16 13:45:51 -08:00
Eddie Hung
8f36013fac
read_xaiger() to use f.read() not readsome()
2019-02-16 08:58:25 -08:00
Eddie Hung
7523c87780
read_aiger() to cope with constant outputs, mixed wideports, do cleaning
2019-02-16 08:44:11 -08:00
Eddie Hung
8d757224ee
read_aiger with more asserts, and call clean
2019-02-15 11:52:05 -08:00
Eddie Hung
c7ef3863f3
Leave FIXME for clean
2019-02-13 17:19:30 -08:00
Eddie Hung
396da54b52
Use module->addLut()
2019-02-13 17:08:32 -08:00
Eddie Hung
13bf036bd6
Use ConstEval to compute LUT masks
2019-02-13 17:00:00 -08:00
Eddie Hung
f0f5d8a5cc
Merge remote-tracking branch 'origin/read_aiger' into xaig
2019-02-13 14:09:36 -08:00
Eddie Hung
06cf0555ee
Merge https://github.com/YosysHQ/yosys into xaig
2019-02-13 14:08:31 -08:00
Clifford Wolf
807b3c7697
Fix sign handling of real constants
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-13 12:36:47 +01:00
Eddie Hung
e9df9a466a
Add support for read_aiger -wideports
2019-02-12 12:58:10 -08:00
Eddie Hung
06ba81d41f
Add support for read_aiger -map
2019-02-12 12:16:37 -08:00
Eddie Hung
77d3627753
Parse 'm' in xaiger
2019-02-12 09:36:22 -08:00
Eddie Hung
6faad18874
Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger
2019-02-12 09:21:46 -08:00
Eddie Hung
a2ae393811
Use module->add{Not,And}Gate() functions
2019-02-12 09:21:15 -08:00
Eddie Hung
0124512f28
Add read_xaiger
2019-02-11 15:19:17 -08:00
Eddie Hung
04c580fde7
Do not break for constraints
2019-02-11 13:28:00 -08:00
Eddie Hung
727ba52504
No increment line_count for binary ANDs
2019-02-11 13:24:21 -08:00
Eddie Hung
bb4164481d
Do not ignore newline after AND in binary AIG
2019-02-11 11:51:44 -08:00
Eddie Hung
8886fa5506
addDff -> addDffGate as per @daveshah1
2019-02-08 13:17:53 -08:00
Eddie Hung
afc3c4b613
Fix tabulation
2019-02-08 13:17:02 -08:00
Eddie Hung
aa66d8f12f
-module_name arg to go before -clk_name
2019-02-08 12:49:55 -08:00
Eddie Hung
391ec75b07
Add missing "[options]" to read_blif help
2019-02-08 12:41:39 -08:00
Eddie Hung
fb8ad440a3
Allow module name to be determined by argument too
2019-02-08 12:40:43 -08:00
Eddie Hung
f1befe1b44
Refactor into AigerReader class
2019-02-08 12:04:26 -08:00
Eddie Hung
2a8cc36578
Parse binary AIG files
2019-02-08 11:45:16 -08:00
Eddie Hung
09d758f0a3
Refactor to parse_aiger_header()
2019-02-08 10:54:31 -08:00
Eddie Hung
36c56bf412
Add comment
2019-02-08 08:37:44 -08:00
Eddie Hung
5e24251a61
Handle reset logic in latches
2019-02-08 08:37:18 -08:00
Eddie Hung
652e414392
Change literal vars from int to unsigned
2019-02-08 08:09:30 -08:00
Eddie Hung
fafa972238
Create clk outside of latch loop
2019-02-08 08:08:49 -08:00
Eddie Hung
02f603ac1a
Handle latch symbols too
2019-02-08 08:05:27 -08:00
Eddie Hung
5a593ff41c
Remove return after log_error
2019-02-08 08:04:48 -08:00
Eddie Hung
6dbeda1807
Add support for symbol tables
2019-02-08 08:03:40 -08:00
Eddie Hung
791f93181d
Stub for binary AIGER
2019-02-08 07:31:04 -08:00
Eddie Hung
40db2f2eb6
Refactor
2019-02-06 14:58:47 -08:00
Eddie Hung
cc0b723484
WIP
2019-02-06 12:19:48 -08:00
Clifford Wolf
17ceab92a9
Bugfix in Verilog string handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-05 12:10:24 +01:00
Clifford Wolf
6d1e7e9403
Remove -m32 Verific eval lib build instructions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-04 15:03:49 +01:00
Clifford Wolf
1eb101a38a
Improve VerificImporter support for writes to asymmetric memories
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-02 15:33:43 +01:00
Clifford Wolf
50b09de033
Fix VerificImporter asymmetric memories error message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-02 15:05:23 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Clifford Wolf
6dad191377
Add "read_ilang -[no]overwrite"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-23 15:45:09 +01:00
Clifford Wolf
fdf7c42181
Fix segfault in AST simplify
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(as proposed by Dan Gisselquist)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 17:49:38 +01:00
Clifford Wolf
3d671630e2
Improve src tagging (using names and attrs) of cells and wires in verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 16:01:22 +01:00
whitequark
4effb38e6d
read_ilang: allow slicing sigspecs.
2018-12-16 17:53:26 +00:00
Sylvain Munaut
58fb2ac818
verilog_parser: Properly handle recursion when processing attributes
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Fixes #737
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-14 12:48:00 +01:00
Clifford Wolf
910d94b212
Verific updates
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:21:50 +01:00
Sylvain Munaut
86ce43999e
Make return value of $clog2 signed
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As per Verilog 2005 - 17.11.1.
Fixes #708
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-24 18:49:23 +01:00
Clifford Wolf
5387ccb041
Set Verific flag vhdl_support_variable_slice=1
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-09 21:03:23 +01:00
Clifford Wolf
719e29404a
Allow square brackets in liberty identifiers
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-05 12:33:33 +01:00
Clifford Wolf
36ea98385f
Add warning for SV "restrict" without "property"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 15:57:17 +01:00
Clifford Wolf
64e0582c29
Various indenting fixes in AST front-end (mostly space vs tab issues)
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-04 10:19:32 +01:00
ZipCPU
39f891aebc
Make and dependent upon LSB only
2018-11-03 13:39:32 -04:00
Clifford Wolf
d86ea6badd
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-11-01 15:25:24 +01:00
Clifford Wolf
5ab58d4930
Fix minor typo in error message
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-25 13:20:00 +02:00
Clifford Wolf
6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error
...
More meaningful SystemVerilog/Verilog parser error messages
2018-10-25 13:18:59 +02:00
Udi Finkelstein
536ae16c3a
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
...
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00
Clifford Wolf
23b69ca32b
Improve read_verilog range out of bounds warning
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-20 23:48:53 +02:00
Ruben Undheim
436e3c0a7c
Refactor code to avoid code duplication + added comments
2018-10-20 16:06:48 +02:00
Ruben Undheim
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
Ruben Undheim
d9a4381012
Fixed memory leak
2018-10-20 11:57:39 +02:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
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Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
Clifford Wolf
93d99559ef
Merge pull request #664 from tklam/ignore-verilog-protect
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Ignore protect endprotect
2018-10-18 10:52:07 +02:00
Clifford Wolf
6ca493b88c
Minor code cleanups in liberty front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-17 12:23:36 +02:00
Clifford Wolf
8395c18cb5
Merge pull request #660 from tklam/parse-liberty-detect-ff-latch
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Handling ff/latch in liberty files
2018-10-17 12:21:17 +02:00
Clifford Wolf
38dbb44fa0
Merge pull request #638 from udif/pr_reg_wire_error
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Fix issue #630
2018-10-17 12:13:18 +02:00
argama
097da32e1a
ignore protect endprotect
2018-10-16 21:33:37 +08:00
Ruben Undheim
736105b046
Handle FIXME for modport members without type directly in front
2018-10-13 20:50:33 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
argama
455638e00d
detect ff/latch before processing other nodes
2018-10-14 01:42:48 +08:00
Ruben Undheim
a36d1701dd
Fix build error with clang
2018-10-12 22:14:49 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Clifford Wolf
9850de405a
Improve Verific importer blackbox handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-07 19:48:55 +02:00
Clifford Wolf
4b0448fc2c
Fix compiler warning in verific.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-05 09:26:10 +02:00
Tom Verbeure
cb214fc01d
Fix for issue 594.
2018-10-02 07:44:23 +00:00
Dan Gisselquist
62424ef3de
Add read_verilog $changed support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-01 19:41:35 +02:00
Clifford Wolf
4d2917447c
Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys
2018-09-30 18:44:07 +02:00
Clifford Wolf
9f9fe94b35
Fix handling of $past 2nd argument in read_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-30 18:43:35 +02:00
Udi Finkelstein
80a07652f2
Fixed issue #630 by fixing a minor typo in the previous commit
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(as well as a non critical minor code optimization)
2018-09-25 00:32:57 +03:00
Clifford Wolf
8fde05dfa5
Add "read_verilog -noassert -noassume -assert-assumes"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-24 20:51:16 +02:00
Clifford Wolf
eb452ffb28
Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-23 10:32:54 +02:00
Udi Finkelstein
c693f595c5
Merge branch 'master' into pr_reg_wire_error
2018-09-18 01:27:01 +03:00
Udi Finkelstein
f6fe73b31f
Fixed remaining cases where we check fo wire reg/wire incorrect assignments
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on Yosys-generated assignments.
In this case, offending code was:
module top(input in, output out);
function func;
input arg;
func = arg;
endfunction
assign out = func(in);
endmodule
2018-09-18 01:23:40 +03:00
Clifford Wolf
5d9d22f66d
Add "verific -L <int>" option
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-04 20:06:10 +02:00
Clifford Wolf
ddc1761f1a
Add "make coverage"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-27 14:22:21 +02:00
Clifford Wolf
4d269f9b25
Merge pull request #610 from udif/udif_specify_round2
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More specify/endspecify fixes
2018-08-23 14:43:25 +02:00
Udi Finkelstein
042b3074f8
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
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This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
2018-08-23 15:26:02 +03:00
Clifford Wolf
408077769f
Add "verific -work" help message
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-22 17:22:24 +02:00
Clifford Wolf
4b02ee9162
Add Verific -work parameter
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-22 13:30:22 +02:00
Udi Finkelstein
fbfc677df3
Fixed all known specify/endspecify issues, without breaking 'make test'.
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Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
2018-08-20 17:27:45 +03:00
Udi Finkelstein
95241c8f4d
Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v ,
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(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
2018-08-20 00:08:08 +03:00
Clifford Wolf
e343f3e6d4
Add "verific -set-<severity> <msg_id>.."
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-16 11:49:17 +02:00
Clifford Wolf
0899a53bee
Verific workaround for VIPER ticket 13851
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-16 11:31:19 +02:00
Udi Finkelstein
28cfc75a90
A few minor enhancements to specify block parsing.
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Just remember specify blocks are parsed but ignored.
2018-08-15 20:14:52 +03:00
Clifford Wolf
67b1026297
Merge pull request #591 from hzeller/virtual-override
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Consistent use of 'override' for virtual methods in derived classes.
2018-08-15 14:05:38 +02:00
Clifford Wolf
d8e40c75eb
Merge pull request #590 from hzeller/remaining-file-error
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Fix remaining log_file_error(); emit dependent file references in new…
2018-08-15 14:01:34 +02:00
Clifford Wolf
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
Clifford Wolf
d71529baa1
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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Detect illegal port declaration, e.g input/output/inout keyword must …
2018-08-15 13:14:23 +02:00
Clifford Wolf
93efbd5d15
Fixed use of char array for string in blifparse error handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-08-08 19:41:47 +02:00
litghost
219f1e9fc9
Report error reason on same line as syntax error.
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Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
2018-08-08 10:22:55 -07:00
litghost
475c2af812
Use log_warning which does not immediately terminate.
2018-08-03 08:05:45 -07:00
litghost
f42d6a9c93
Add BLIF parsing support for .conn and .cname
2018-08-02 14:36:56 -07:00
Clifford Wolf
e275692e84
Verific: Produce errors for instantiating unknown module
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Because if the unknown module is connected to any constants, Verific will
actually break all constants in the same module, even if they have nothing
to do structurally with that instance of an unknown module.
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-22 18:44:05 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Henner Zeller
3101b9b8c9
Fix remaining log_file_error(); emit dependent file references in new line.
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There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
2018-07-20 18:52:52 -07:00
Henner Zeller
68b5d0c3b1
Convert more log_error() to log_file_error() where possible.
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Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
2018-07-20 09:37:44 -07:00
Henner Zeller
b5ea598ef6
Use log_file_warning(), log_file_error() functions.
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Wherever we can report a source-level location.
2018-07-20 08:19:06 -07:00
Henner Zeller
1a60126a34
Provide source-location logging.
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o Provide log_file_warning() and log_file_error() that prefix the log
message with <filename>:<lineno>: to be easily picked up by IDEs that
need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
2018-07-19 10:22:02 -07:00
Clifford Wolf
65234d4b24
Fix handling of eventually properties in verific importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-17 12:43:30 +02:00
Clifford Wolf
5041ed2f7d
Fix verific -vlog-incdir and -vlog-libdir handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 18:47:42 +02:00
Clifford Wolf
f897af626d
Fix "read -incdir"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 16:48:09 +02:00
Clifford Wolf
f39b897545
Add "read -incdir"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-07-16 15:32:26 +02:00
Clifford Wolf
8b92ddb9d2
Fix verific eventually handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-29 19:24:58 +02:00
Clifford Wolf
0404cf61d5
Add verific support for eventually properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-29 19:21:04 +02:00
Clifford Wolf
ebf0f003d3
Add "verific -formal" and "read -formal"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-29 10:02:27 +02:00
Clifford Wolf
afedb2d03e
Add "read -sv -D" support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-28 23:58:15 +02:00
Clifford Wolf
07e616900c
Add "read -undef"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-28 23:43:38 +02:00
Clifford Wolf
fe2ee833e1
Fix handling of signed memories
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-28 16:57:03 +02:00
Clifford Wolf
848c3c5c88
Add YOSYS_NOVERIFIC env variable for temporarily disabling verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-22 20:40:22 +02:00
Clifford Wolf
d412b17259
Add simplified "read" command, enable extnets in implicit Verific import
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-21 16:56:55 +02:00
Clifford Wolf
5f2bc1ce76
Add automatic verific import in hierarchy command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-20 23:45:01 +02:00
Clifford Wolf
0ff0ce4973
Bugfix in liberty parser (as suggested by aiju in #569 )
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-15 18:56:44 +02:00
Udi Finkelstein
8b7580b0a1
Detect illegal port declaration, e.g input/output/inout keyword must be the first.
2018-06-06 22:27:25 +03:00
Udi Finkelstein
73d426bc87
Modified errors into warnings
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No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
Clifford Wolf
4372cf690d
Add (* gclk *) attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 13:25:42 +02:00
Clifford Wolf
9a946c207f
Add comment to VIPER #13453 work-around
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-28 13:36:35 +02:00
Clifford Wolf
001c9f1d45
Fix Verific handling of single-bit anyseq/anyconst wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-25 15:41:45 +02:00
Clifford Wolf
251562a491
Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-24 18:13:38 +02:00
Clifford Wolf
4d645f0fce
Fix verific handling of anyconst/anyseq attributes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-24 17:07:06 +02:00
Jim Paris
4a229e5b95
Support SystemVerilog `` extension for macros
2018-05-17 00:09:56 -04:00
Jim Paris
872d8d49e9
Skip spaces around macro arguments
2018-05-17 00:06:49 -04:00
Clifford Wolf
a7281930c5
Fix handling of anyconst/anyseq attrs in VHDL code via Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 19:27:00 +02:00
Sergiusz Bazanski
7d076f071e
Also interpret '&' in liberty functions
2018-05-12 20:55:31 +02:00
Clifford Wolf
24e6401617
Further improve handling of zero-length SVA consecutive repetition
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-05 14:32:04 +02:00
Clifford Wolf
3e67497ec2
Fix handling of zero-length SVA consecutive repetition
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-05 13:58:01 +02:00
Clifford Wolf
a572b49538
Replace -ignore_redef with -[no]overwrite
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-03 15:25:59 +02:00
Dan Gisselquist
e060375f23
Support more character literals
2018-05-03 12:35:01 +02:00
Clifford Wolf
2d7f3123f0
Add statement labels for immediate assertions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-13 11:52:28 +02:00
Clifford Wolf
66ffc99695
Allow "property" in immediate assertions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-12 14:28:28 +02:00
Clifford Wolf
617c60cea6
Add PRIM_HDL_ASSERTION support to Verific importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-07 18:38:42 +02:00
Clifford Wolf
0ac768f9df
Fix handling of $global_clocking in Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-06 21:23:47 +02:00
Clifford Wolf
5ea2c53604
Add read_verilog anyseq/anyconst/allseq/allconst attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-06 14:35:11 +02:00
Clifford Wolf
278685b084
Add Verific anyseq/anyconst/allseq/allconst attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-06 14:19:55 +02:00
Clifford Wolf
ab8db2c168
Add "verific -autocover"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-06 14:10:57 +02:00
makaimann
0c404b1f63
Set RAM runtime flags for Verific frontend
2018-04-05 17:38:08 -07:00
Clifford Wolf
93985d91b1
Remove left-over log_ping debug commands.. oops.
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-31 14:23:57 +02:00
Udi Finkelstein
6378e2cd46
First draft of Verilog parser support for specify blocks and parameters.
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The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
2018-03-27 14:34:00 +02:00
Clifford Wolf
315d5e32bf
Fix handling of unclocked immediate assertions in Verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-26 13:04:10 +02:00
Clifford Wolf
e7862d4f64
Update todo for more features to verificsva.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-16 15:48:48 +01:00
Clifford Wolf
38596ce68f
Update todo for more features to verificsva.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-16 12:16:52 +01:00
Clifford Wolf
462e9f7bd4
Add todo for more features to verificsva.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-16 12:15:36 +01:00
Clifford Wolf
7cf9d88028
Improve import of memories via Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-15 18:20:37 +01:00
Clifford Wolf
bf402a806a
Fix handling of SV compilation units in Verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-14 20:22:11 +01:00
Udi Finkelstein
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
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It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
Clifford Wolf
307c16a309
Fix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEAT
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-10 16:24:01 +01:00
Clifford Wolf
ce37b6d730
Fix variable name typo in verificsva.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-10 14:33:42 +01:00
Clifford Wolf
da216937b1
Add support for trivial SVA sequences and properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-10 14:32:01 +01:00
Clifford Wolf
a15208f301
Use Verific hier_tree component for elaboration
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-08 13:26:33 +01:00
Clifford Wolf
a4bbfd2d15
Fix Verific handling of "assert property (..);" in always block
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-07 20:06:02 +01:00
Clifford Wolf
92d5f4db6f
Add "verific -import -V"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-07 19:40:34 +01:00
Clifford Wolf
252627fc54
Set Verific db_preserve_user_nets flag
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-07 18:08:03 +01:00
Clifford Wolf
dcc4a18d5a
Update comment about supported SVA in verificsva.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 15:47:33 +01:00
Clifford Wolf
03b49654b1
Add SVA NON_CONSECUTIVE_REPEAT and GOTO_REPEAT support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 15:39:46 +01:00
Clifford Wolf
7bb83ae9f2
Add SVA first_match() support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 15:06:35 +01:00
Clifford Wolf
78f2cca2d9
Add SVA within support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 14:41:27 +01:00
Clifford Wolf
5555292ce2
Add support for SVA sequence intersect
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 14:26:57 +01:00
Clifford Wolf
d86e875f0f
Add get_fsm_accept_reject for parsing SVA properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 11:50:38 +01:00
Clifford Wolf
588ce0e34a
Simplified SVA "until" handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-06 01:51:42 +01:00
Clifford Wolf
480e8e676a
Add proper SVA seq.triggered support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 19:29:26 +01:00
Clifford Wolf
8dcf3d0c76
Add Verific SVA support for "seq and seq" expressions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 15:08:21 +01:00
Clifford Wolf
9ab2498c55
Refactor Verific SVA importer property parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 14:29:48 +01:00
Clifford Wolf
261cf706f4
Add VerificClocking class and refactor Verific DFF handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 13:48:53 +01:00
Clifford Wolf
707ddb77bc
Add SVA support for sequence OR
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-03 16:34:28 +01:00
Clifford Wolf
cabc3c59e0
Fix handling of SVA "until seq.triggered" properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-02 18:17:10 +01:00
Clifford Wolf
ab791e61b3
Update SVA cheat sheet in verificsva.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-02 16:05:56 +01:00
Clifford Wolf
4e5f1f59d6
Fix in Verific SVA importer handling of until_with
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-01 19:37:36 +01:00
Clifford Wolf
9a2a8cd97b
Fixes and improvements in Verific SVA importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-01 11:40:43 +01:00
Clifford Wolf
3c49e3c5b3
Add $rose/$fell support to Verific bindings
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-01 10:12:15 +01:00
Clifford Wolf
5ac3ee858a
Add support for PRIM_SVA_UNTIL to new SVA importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-28 15:32:17 +01:00
Clifford Wolf
8a1d6ccf0c
Add DFSM generator to verific SVA importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-28 15:05:33 +01:00
Clifford Wolf
15902d495f
Continue refactoring of Verific SVA importer code
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-28 11:45:04 +01:00
Clifford Wolf
25e33d7ab8
Major redesign of Verific SVA importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-27 20:33:15 +01:00
Clifford Wolf
b6fbeb0969
Add handling of verific OPER_REDUCE_NOR
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-26 15:26:01 +01:00
Clifford Wolf
2aeb4d4e12
Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-26 15:20:27 +01:00
Clifford Wolf
9cd9f5fc78
Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-26 15:02:03 +01:00
Clifford Wolf
d1cb5150aa
Add "SVA syntax cheat sheet" comment to verificsva.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-26 14:31:58 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
2521ed305e
Add Verific SVA support for ranges in repetition operator
2018-02-22 12:37:30 +01:00
Clifford Wolf
6d12c83d36
Add support for SVA throughout via Verific
2018-02-21 13:09:47 +01:00
Clifford Wolf
5c6247dfa6
Add support for SVA sequence concatenation ranges via verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-18 16:35:06 +01:00
Clifford Wolf
9d963cd29c
Add support for SVA until statements via Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-18 14:57:52 +01:00
Clifford Wolf
5fa2aa2741
Move Verific SVA importer to extra C++ source file
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-18 13:52:49 +01:00
Clifford Wolf
c4bf34f6ce
Merge Verific SVA preprocessor and SVA importer
2018-02-18 13:28:08 +01:00
Clifford Wolf
68a829dbcd
Merge branch 'master' of github.com:cliffordwolf/yosys
2018-02-16 14:22:11 +01:00
Clifford Wolf
2c95dfcb5b
Improve handling of "bus" pins in liberty front-end (some files use bus.pin.direction)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-15 17:36:08 +01:00
Clifford Wolf
bc8ab3ab44
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
2018-02-15 15:26:37 +01:00
Clifford Wolf
6c00e064e2
Fix single-bit $stable handling in verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-01 12:51:49 +01:00
Clifford Wolf
9af40faa0b
Add Verific attribute handling for assert/assume/cover/live/fair cells
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-31 19:06:51 +01:00
Clifford Wolf
675f53abbb
Fix permissions on verific vdb files
2018-01-28 18:52:01 +01:00
Clifford Wolf
1d8161b432
Fixed handling of synchronous and asynchronous assertion/assumption/cover in verific bindings
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-23 17:42:40 +01:00
Clifford Wolf
a96c775a73
Add support for "yosys -E"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-07 16:36:13 +01:00
Clifford Wolf
26c4323d48
Merge pull request #479 from Fatsie/latch_without_data
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Some standard cell libraries include a latch with only set/reset.
2018-01-05 23:00:28 +01:00
Clifford Wolf
c80315cea4
Bugfix in hierarchy handling of blackbox module ports
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-01-05 13:28:45 +01:00
Staf Verhaegen
5126c6f22b
Some standard cell libraries include a latch with only set/reset.
2018-01-03 21:36:02 +00:00
Clifford Wolf
34005348b6
Bugfix in verilog_defaults argument parser
2017-12-24 17:21:37 +01:00
Clifford Wolf
ba90e08398
Add support for Verific PRIM_SVA_NOT properties
2017-12-10 01:10:03 +01:00
Clifford Wolf
e4a4c0e10c
Add Verific OPER_SVA_STABLE support
2017-12-10 00:59:44 +01:00
Clifford Wolf
27916105a9
Refactoring Verific SVA rewriter
2017-12-10 00:26:26 +01:00
Clifford Wolf
8364f509e3
Fix error handling for nested always/initial
2017-12-02 18:52:05 +01:00
Clifford Wolf
777f2881d8
Add Verilog "automatic" keyword (ignored in synthesis)
2017-11-23 08:51:38 +01:00
Clifford Wolf
5b6e52118c
Accept real-valued delay values
2017-11-18 10:01:30 +01:00
William D. Jones
abc5b4b8ce
Accommodate Windows-style paths during include-file processing.
2017-11-14 16:16:24 -05:00
Clifford Wolf
a8cf431d9c
Remove vhdl2verilog
2017-10-25 14:50:22 +02:00
Clifford Wolf
0a31a0b3ae
Remove all PSL support code from verific.cc
2017-10-20 13:14:04 +02:00
Clifford Wolf
1954c78ea7
Add "verific -vlog-libdir"
2017-10-13 20:23:19 +02:00
Clifford Wolf
e7a3c47cc7
Add "verific -vlog-incdir" and "verific -vlog-define"
2017-10-13 20:12:51 +02:00
Clifford Wolf
05068af880
Update Verific README
2017-10-13 17:11:53 +02:00
Clifford Wolf
bc5cc4e103
Add Verific fairness/liveness support
2017-10-12 12:00:09 +02:00
Clifford Wolf
12c10892e6
Merge branch 'master' of github.com:cliffordwolf/yosys
2017-10-10 15:16:45 +02:00
Clifford Wolf
c10e96c9ec
Start work on pre-processor for Verific SVA properties
2017-10-10 15:16:39 +02:00
Clifford Wolf
bc80426d45
Remove some dead code
2017-10-10 12:00:48 +02:00
Clifford Wolf
caa78388cd
Allow $past, $stable, $rose, $fell in $global_clock blocks
2017-10-10 11:59:32 +02:00
Clifford Wolf
fc3378916d
Improve handling of Verific errors
2017-10-05 14:38:32 +02:00
Clifford Wolf
ee56a887b6
Improve Verific error handling, check VHDL static asserts
2017-10-04 18:56:28 +02:00
Clifford Wolf
b92ff2706e
Fix nasty bug in Verific bindings
2017-10-04 17:23:42 +02:00
Clifford Wolf
a381188b92
Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys
2017-10-03 18:23:45 +02:00
Udi Finkelstein
eb40278a16
Turned a few member functions into const, esp. dumpAst(), dumpVlog().
2017-09-30 07:37:38 +03:00
Udi Finkelstein
72a08eca3d
Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution
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(Oreilly 'Flex & Bison' page 189)
2017-09-30 06:39:07 +03:00
Clifford Wolf
dbfd8460a9
Allow $size and $bits in verilog mode, actually check test case
2017-09-29 11:56:43 +02:00
Udi Finkelstein
e951ac0dfb
$size() now works correctly for all cases!
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It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
2017-09-26 20:34:24 +03:00
Udi Finkelstein
6ddc6a7af4
$size() seems to work now with or without the optional parameter.
...
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 19:18:25 +03:00
Udi Finkelstein
7e391ba904
enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog
2017-09-26 09:19:56 +03:00
Udi Finkelstein
2dea42e903
Added $bits() for memories as well.
2017-09-26 09:11:25 +03:00
Udi Finkelstein
17f8b41605
$size() now works with memories as well!
2017-09-26 08:36:45 +03:00
Udi Finkelstein
64eb8f29ad
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 06:25:42 +03:00
Clifford Wolf
30396270a2
Increase maximum LUT size in blifparse to 12 bits
2017-09-27 15:27:42 +02:00
Clifford Wolf
91d9c50bb3
Parse reals as string in JSON front-end
2017-09-26 14:37:03 +02:00
Clifford Wolf
2c04d883b1
Minor coding style fix
2017-09-26 13:50:14 +02:00
Clifford Wolf
cb1d439d10
Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master
2017-09-26 13:48:13 +02:00
Clifford Wolf
2cc09161ff
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
2017-09-26 01:52:59 +02:00
combinatorylogic
64ca0be971
Adding support for string macros and macros with arguments after include
2017-09-21 18:25:02 +01:00
Robert Ou
366ce87cff
json: Parse inout correctly rather than as an output
2017-08-14 12:09:03 -07:00
Clifford Wolf
15073790bf
Add merging of "past FFs" to verific importer
2017-07-29 00:10:38 +02:00
Clifford Wolf
d4b9602cbd
Add minimal support for PSL in VHDL via Verific
2017-07-28 17:39:49 +02:00
Clifford Wolf
5a828fff34
Improve Verific HDL language options
2017-07-28 15:32:54 +02:00
Clifford Wolf
acd6cfaf67
Fix handling of non-user-declared Verific netbus
2017-07-28 11:31:27 +02:00
Clifford Wolf
c1cfca8f54
Improve Verific SVA importer
2017-07-27 14:05:09 +02:00
Clifford Wolf
2336d5508b
Add log_warning_noprefix() API, Use for Verific warnings and errors
2017-07-27 12:17:04 +02:00
Clifford Wolf
d9641621d9
Add "verific -import -n" and "verific -import -nosva"
2017-07-27 11:54:45 +02:00
Clifford Wolf
90d8329f64
Improve Verific SVA import: negedge and $past
2017-07-27 11:40:07 +02:00
Clifford Wolf
147ff96ba3
Improve Verific SVA importer
2017-07-27 10:39:39 +02:00
Clifford Wolf
530040ba6f
Improve Verific bindings (mostly related to SVA)
2017-07-26 18:00:01 +02:00
Clifford Wolf
abd3b4e8e7
Improve "help verific" message
2017-07-25 15:13:22 +02:00
Clifford Wolf
6dbe1d4c92
Add "verific -extnets"
2017-07-25 14:53:11 +02:00
Clifford Wolf
c97c92e4ec
Improve "verific -all" handling
2017-07-25 13:33:25 +02:00
Clifford Wolf
41be530c4e
Add "verific -import -d <dump_file"
2017-07-24 13:57:16 +02:00
Clifford Wolf
92d3aad670
Add "verific -import -flatten" and "verific -import -v"
2017-07-24 11:29:06 +02:00
Clifford Wolf
5be535517c
Add "verific -import -k"
2017-07-22 16:16:44 +02:00
Clifford Wolf
2785aaffeb
Improve docs for verific bindings, add simply sby example
2017-07-22 11:58:51 +02:00
Clifford Wolf
36cf18ac4c
Fix "read_blif -wideports" handling of cells with wide ports
2017-07-21 16:21:12 +02:00
Clifford Wolf
26766da343
Add a paragraph about pre-defined macros to read_verilog help message
2017-07-21 14:34:53 +02:00
Clifford Wolf
9557fd2a36
Add attributes and parameter support to JSON front-end
2017-07-10 13:17:38 +02:00
Clifford Wolf
4b2d1fe688
Add JSON front-end
2017-07-08 16:40:40 +02:00
Clifford Wolf
28039c3063
Add Verific Release information to log
2017-07-04 20:01:30 +02:00
Clifford Wolf
8f8baccfde
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg"
2017-06-07 12:30:24 +02:00
Clifford Wolf
129984e115
Fix handling of Verilog ~& and ~| operators
2017-06-01 12:43:21 +02:00
Clifford Wolf
e91548b33e
Add support for localparam in module header
2017-04-30 17:20:30 +02:00
Clifford Wolf
f0db8ffdbc
Add support for `resetall compiler directive
2017-04-26 16:09:41 +02:00
Clifford Wolf
088f9c9cab
Fix verilog pre-processor for multi-level relative includes
2017-03-14 17:30:20 +01:00
Clifford Wolf
5b3b5ffc8c
Allow $anyconst, etc. in non-formal SV mode
2017-03-01 10:47:05 +01:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
00dba4c197
Add support for SystemVerilog unique, unique0, and priority case
2017-02-23 16:33:19 +01:00
Clifford Wolf
1e927a51d5
Preserve string parameters
2017-02-23 15:39:13 +01:00
Clifford Wolf
34d4e72132
Added SystemVerilog support for ++ and --
2017-02-23 11:21:33 +01:00
Clifford Wolf
4fb8007171
Fix incorrect "incompatible re-declaration of wire" error in tasks/functions
2017-02-14 15:10:59 +01:00
Clifford Wolf
cdb6ceb8c6
Add support for verific mem initialization
2017-02-11 15:57:36 +01:00
Clifford Wolf
c449f4b86f
Fix another stupid bug in the same line
2017-02-11 11:47:51 +01:00
Clifford Wolf
fa4a7efe15
Add verific support for initialized variables
2017-02-11 11:40:18 +01:00
Clifford Wolf
0b7aac645c
Improve handling of Verific warnings and error messages
2017-02-11 11:39:50 +01:00
Clifford Wolf
eb7b18e897
Fix extremely stupid typo
2017-02-11 11:09:07 +01:00
Clifford Wolf
848062088c
Add checker support to verilog front-end
2017-02-09 13:51:44 +01:00
Clifford Wolf
2ca8d483dd
Add "rand" and "rand const" verific support
2017-02-09 12:53:46 +01:00
Clifford Wolf
ef4a28e112
Add SV "rand" and "const rand" support
2017-02-08 14:38:15 +01:00
Clifford Wolf
1d1f56a361
Add PSL parser mode to verific front-end
2017-02-08 10:40:33 +01:00
Clifford Wolf
7e0b776a79
Add "read_blif -wideports"
2017-02-06 14:48:03 +01:00
Clifford Wolf
6abf79eb28
Further improve cover() support
2017-02-04 17:02:13 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
911c44d164
Add assert/assume support to verific front-end
2017-02-04 13:36:00 +01:00
Clifford Wolf
fea528280b
Add "enum" and "typedef" lexer support
2017-01-17 17:33:52 +01:00
Clifford Wolf
78f65f89ff
Fix bug in AstNode::mem2reg_as_needed_pass2()
2017-01-15 13:52:50 +01:00
Clifford Wolf
2d32c6c4f6
Fixed handling of local memories in functions
2017-01-05 13:19:03 +01:00
Clifford Wolf
81a9ee2360
Added handling of local memories and error for local decls in unnamed blocks
2017-01-04 16:03:04 +01:00
Clifford Wolf
dfb461fe52
Added Verilog $rtoi and $itor support
2017-01-03 17:40:58 +01:00
Clifford Wolf
3886669ab6
Added "verilog_defines" command
2016-12-15 17:49:28 +01:00
Clifford Wolf
ecdc22b06c
Added support for macros as include file names
2016-11-28 14:50:17 +01:00
Clifford Wolf
c7f6fb6e17
Bugfix in "read_verilog -D NAME=VAL" handling
2016-11-28 14:45:05 +01:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
a926a6afc2
Remember global declarations and defines accross read_verilog calls
2016-11-15 12:42:43 +01:00
Clifford Wolf
2874914bcb
Fixed anonymous genblock object names
2016-11-04 07:46:30 +01:00
Clifford Wolf
56e2bb88ae
Some fixes in handling of signed arrays
2016-11-01 23:17:43 +01:00
Clifford Wolf
aa72262330
Added avail params to ilang format, check module params in 'hierarchy -check'
2016-10-22 11:05:49 +02:00
Clifford Wolf
042b67f024
No limit for length of lines in BLIF front-end
2016-10-19 12:44:58 +02:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
8f5bf6de32
Added liberty parser support for types within cell decls
2016-09-23 13:53:23 +02:00
Clifford Wolf
aaa99c35bd
Added $past, $stable, $rose, $fell SVA functions
2016-09-19 01:30:07 +02:00
Clifford Wolf
13a03b84d4
Added support for bus interfaces to "read_liberty -lib"
2016-09-18 18:48:59 +02:00
Clifford Wolf
ab18e9df7c
Added assertpmux
2016-09-07 00:28:01 +02:00
Clifford Wolf
d55a93b39f
Bugfix in parsing of BLIF latch init values
2016-09-06 17:35:06 +02:00
Clifford Wolf
97583ab729
Avoid creation of bogus initial blocks for assert/assume in always @*
2016-09-06 17:34:42 +02:00
Clifford Wolf
aa25a4cec6
Added $anyconst support to yosys-smtbmc
2016-08-30 19:27:42 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
1276c87a56
Added read_verilog -norestrict -assume-asserts
2016-08-26 23:35:27 +02:00
Clifford Wolf
4be4969bae
Improved verilog parser errors
2016-08-25 11:44:37 +02:00
Clifford Wolf
cd18235f30
Added SV "restrict" keyword
2016-08-24 15:30:08 +02:00
Clifford Wolf
450f6f59b4
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
Clifford Wolf
82a4a0230f
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
Clifford Wolf
dbdd8927e7
Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()
2016-08-21 13:18:09 +02:00
Clifford Wolf
fe9315b7a1
Fixed finish_addr handling in $readmemh/$readmemb
2016-08-20 13:47:46 +02:00
Clifford Wolf
f6629b9c29
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
2016-08-19 18:38:25 +02:00
Clifford Wolf
e9fe57c75e
Only allow posedge/negedge with 1 bit wide signals
2016-08-10 19:32:11 +02:00
Clifford Wolf
7f755dec75
Fixed bug in parsing real constants
2016-08-06 13:16:23 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
a7b0769623
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
Clifford Wolf
5b944ef11b
Fixed a verilog parser memory leak
2016-07-25 16:37:58 +02:00
Clifford Wolf
7a67add95d
Fixed parsing of empty positional cell ports
2016-07-25 12:48:03 +02:00
Clifford Wolf
9aae1d1e8f
No tristate warning message for "read_verilog -lib"
2016-07-23 11:56:53 +02:00
Clifford Wolf
7fef5ff104
Using $initstate in "initial assume" and "initial assert"
2016-07-21 14:37:28 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Clifford Wolf
9a101dc1f7
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
Ruben Undheim
545bcb37e8
Allow defining input ports as "input logic" in SystemVerilog
2016-06-20 20:16:37 +02:00
Clifford Wolf
9bca8ccd40
Merge branch 'sv_packages' of https://github.com/rubund/yosys
2016-06-19 15:48:40 +02:00
Ruben Undheim
a8200a773f
A few modifications after pull request comments
...
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
2016-06-18 14:23:38 +02:00
Clifford Wolf
9e28290b0f
Added "read_blif -sop"
2016-06-18 12:33:13 +02:00
Ruben Undheim
178ff3e7f6
Added support for SystemVerilog packages with localparam definitions
2016-06-18 10:53:55 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
766032c5f8
Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
2016-05-27 17:55:03 +02:00
Clifford Wolf
ee071586c5
Fixed access-after-delete bug in mem2reg code
2016-05-27 17:25:33 +02:00
Clifford Wolf
e9ceec26ff
fixed typos in error messages
2016-05-27 16:37:36 +02:00
Clifford Wolf
060bf4819a
Small improvements in Verilog front-end docs
2016-05-20 16:21:35 +02:00
Clifford Wolf
570014800a
Include <cmath> in yosys.h
2016-05-08 10:50:39 +02:00
Clifford Wolf
779e2cc819
Added support for "active high" and "active low" latches in BLIF front-end
2016-04-22 18:02:55 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
5a09fa4553
Fixed handling of parameters and const functions in casex/casez pattern
2016-04-21 15:31:54 +02:00
Clifford Wolf
5328a85149
Do not set "nosync" on task outputs, fixes #134
2016-03-24 12:16:47 +01:00
Clifford Wolf
4f0d4899ce
Added support for $stop system task
2016-03-21 16:19:51 +01:00
Clifford Wolf
e5d42ebb4d
Added $display %m support, fixed mem leak in $display, fixes #128
2016-03-19 11:51:13 +01:00
Clifford Wolf
ef4207d5ad
Fixed localparam signdness, fixes #127
2016-03-18 12:15:00 +01:00
Clifford Wolf
b6d08f39ba
Set "nosync" attribute on internal task/function wires
2016-03-18 10:53:29 +01:00
Clifford Wolf
33c10350b2
Fixed Verilog parser fix and more similar improvements
2016-03-15 12:22:31 +01:00
Andrew Becker
81d4e9e7c1
Use left-recursive rule for cell_port_list in Verilog parser.
2016-03-15 12:03:40 +01:00
Clifford Wolf
35a6ad4cc1
Fixed typos in verilog_defaults help message
2016-03-10 11:14:51 +01:00
Clifford Wolf
22c549ab37
Fixed BLIF parser for empty port assignments
2016-02-24 09:16:43 +01:00
Clifford Wolf
bcc873b805
Fixed some visual studio warnings
2016-02-13 17:31:24 +01:00
Clifford Wolf
7bd329afa0
Support for more Verific primitives (patch I got per email)
2016-02-13 08:19:30 +01:00
Clifford Wolf
6a27cbe5b1
Bugfix in Verific front-end
2016-02-03 08:59:57 +01:00
Clifford Wolf
4a3e1ded1e
Updated verific build instructions
2016-02-02 19:50:17 +01:00
Clifford Wolf
ba407da187
Added addBufGate module method
2016-02-02 11:26:07 +01:00
Rick Altherr
34969d4140
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()
2016-01-31 09:20:16 -08:00
Clifford Wolf
5e90a78466
Various improvements in BLIF front-end
2015-12-20 13:12:24 +01:00
Clifford Wolf
4a697accd4
Fixed oom bug in ilang parser
2015-11-29 20:30:32 +01:00
Clifford Wolf
32f5ee117c
Fixed performance bug in ilang parser
2015-11-27 19:46:47 +01:00
Clifford Wolf
ab2d8e5c8c
Added PRIM_DLATCHRS support to verific front-end
2015-11-24 12:16:19 +01:00
Clifford Wolf
c86fbae3d1
Fixed handling of re-declarations of wires in tasks and functions
2015-11-23 17:09:57 +01:00
Clifford Wolf
415e0a1b90
Fixed performance bug in Verific importer
2015-11-16 12:38:56 +01:00
Clifford Wolf
b18f3a2974
Changes for Verific 3.16_484_32_151112
2015-11-12 19:28:14 +01:00
Clifford Wolf
7ae3d1b5a9
More bugfixes in handling of parameters in tasks and functions
2015-11-12 13:02:36 +01:00
Clifford Wolf
34f2b84fb6
Fixed handling of parameters and localparams in functions
2015-11-11 10:54:35 +01:00
Clifford Wolf
207736b4ee
Import more std:: stuff into Yosys namespace
2015-10-25 19:30:49 +01:00
Clifford Wolf
5308c1e02a
Fixed bug in verilog parser
2015-10-15 15:19:23 +02:00
Clifford Wolf
f13e387321
SystemVerilog also has assume(), added implicit -D FORMAL
2015-10-13 14:21:20 +02:00
Clifford Wolf
ba4cce9f19
Added support for "parameter" and "localparam" in global context
2015-10-07 14:59:08 +02:00
Clifford Wolf
e51dcc83d0
Fixed complexity of assigning to vectors in constant functions
2015-10-01 12:15:35 +02:00
Clifford Wolf
9caeadf797
Fixed detection of unconditional $readmem[hb]
2015-09-30 15:46:51 +02:00
Clifford Wolf
f9d7df0869
Bugfixes in $readmem[hb]
2015-09-25 13:49:48 +02:00
Clifford Wolf
b2544cfcf7
Fixed segfault in AstNode::asReal
2015-09-25 12:38:01 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
1b8cb9940e
Fixed AstNode::mkconst_bits() segfault on zero-sized constant
2015-09-24 11:21:20 +02:00
Clifford Wolf
e2e092b144
Added read_verilog -nodpi
2015-09-23 08:23:38 +02:00
Clifford Wolf
089c1e176f
Bugfix in handling of multi-dimensional memories
2015-09-23 07:56:17 +02:00
Clifford Wolf
559929e341
Warning for $display/$write outside initial block
2015-09-23 07:16:03 +02:00
Clifford Wolf
b845b77f86
Fixed support for $write system task
2015-09-23 07:10:56 +02:00
Clifford Wolf
a3a13cce32
Fixed detection of "task foo(bar);" syntax error
2015-09-22 21:34:21 +02:00
Clifford Wolf
6176f4d081
Fixed multi-level prefix resolving
2015-09-22 20:52:02 +02:00
Clifford Wolf
4b8200eb49
Fixed segfault on invalid verilog constant 1'b_
2015-09-22 08:13:09 +02:00
Andrew Zonenberg
c469f22144
Improvements to $display system task
2015-09-19 10:33:37 +02:00
Clifford Wolf
9db05d17fe
Added AST_INITIAL checks for $finish and $display
2015-09-18 09:50:57 +02:00
Andrew Zonenberg
7141f65533
Initial implementation of $display()
2015-09-18 09:36:46 +02:00
Andrew Zonenberg
e446e651cb
Initial implementation of $finish()
2015-09-18 09:30:25 +02:00
Clifford Wolf
b10ea0550d
gcc-4.6 build fixes
2015-09-01 12:51:23 +02:00
Clifford Wolf
eb38722e98
Fixed handling of memory read without address
2015-08-22 14:46:42 +02:00
Clifford Wolf
a7ab9172f9
Small corrections to const2ast warning messages
2015-08-17 16:22:53 +02:00
Florian Zeitz
0491042849
Check base-n literals only contain valid digits
2015-08-17 15:37:33 +02:00
Florian Zeitz
64ccbf8510
Warn on literals exceeding the specified bit width
2015-08-17 15:27:35 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Larry Doolittle
022f570563
Keep gcc from complaining about uninitialized variables
2015-08-14 23:26:49 +02:00
Clifford Wolf
0350074819
Re-created command-reference-manual.tex, copied some doc fixes to online help
2015-08-14 11:27:19 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
45ee2ba3b8
Fixed handling of [a-fxz?] in decimal constants
2015-08-11 11:32:37 +02:00
Marcus Comstedt
c836faae3e
Add -noautowire option to verilog frontend
2015-08-01 12:16:54 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
4513ff1b85
Fixed nested mem2reg
2015-07-29 16:37:08 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
13983e8318
Fixed handling of parameters with reversed range
2015-06-08 14:03:06 +02:00
Clifford Wolf
99b8746d27
Fixed signedness of genvar expressions
2015-05-29 20:08:00 +02:00
Clifford Wolf
08a4af3cde
Improvements in BLIF front-end
2015-05-24 08:03:21 +02:00
Clifford Wolf
6061b7bd58
bugfix in blif front-end
2015-05-18 11:15:49 +02:00
Clifford Wolf
3ecb2bf067
Improved .latch support in BLIF front-end
2015-05-17 18:58:24 +02:00
Clifford Wolf
2cc4e75914
Added read_blif command
2015-05-17 15:25:03 +02:00
Clifford Wolf
e5116eeb77
Generalized blifparse API
2015-05-17 15:10:37 +02:00
Clifford Wolf
7dad017c9c
abc/blifparse files reorganization
2015-05-17 14:44:28 +02:00
Clifford Wolf
61512b6f41
Verific build fixes
2015-05-17 08:19:52 +02:00
Clifford Wolf
7ff802e199
Verilog front-end: define `BLACKBOX in -lib mode
2015-04-19 21:30:46 +02:00
Clifford Wolf
a923a63a89
Ignore celldefine directive in verilog front-end
2015-03-25 19:46:12 +01:00
Clifford Wolf
422794c584
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
2015-03-01 11:20:22 +01:00
Clifford Wolf
1f1deda888
Added non-std verilog assume() statement
2015-02-26 18:47:39 +01:00
Clifford Wolf
d5ce9a32ef
Added deep recursion warning to AST simplify
2015-02-20 10:33:20 +01:00
Clifford Wolf
dc1a0f06fc
Parser support for complex delay expressions
2015-02-20 10:21:36 +01:00
Clifford Wolf
e0e6d130cd
YosysJS stuff
2015-02-19 13:36:54 +01:00
Clifford Wolf
c2ba4fb2fd
Convert floating point cell parameters to strings
2015-02-18 23:35:23 +01:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
7f1a1759d7
Added "read_verilog -nomeminit" and "nomeminit" attribute
2015-02-14 11:21:12 +01:00
Clifford Wolf
a8e9d37c14
Creating $meminit cells in verilog front-end
2015-02-14 10:49:30 +01:00
Clifford Wolf
ef151b0b30
Fixed handling of "//" in filenames in verilog pre-processor
2015-02-14 08:41:03 +01:00
Clifford Wolf
cd919abdf1
Added AstNode::simplify() recursion counter
2015-02-13 12:33:12 +01:00
Clifford Wolf
4f68a77e3f
Improved read_verilog support for empty behavioral statements
2015-02-10 12:17:29 +01:00
Clifford Wolf
234a45a3d5
Ignore explicit assignments to constants in HDL code
2015-02-08 00:58:03 +01:00
Clifford Wolf
c8305e3a6d
Fixed a bug with autowire bit size
...
(removed leftover from when we tried to auto-size the wires)
2015-02-08 00:48:23 +01:00
Clifford Wolf
2a9ad48eb6
Added ENABLE_NDEBUG makefile options
2015-01-24 12:16:46 +01:00
Clifford Wolf
df9d096a7d
Ignoring more system task and functions
2015-01-15 13:08:19 +01:00
Clifford Wolf
a588a4a5c9
Fixed handling of "input foo; reg [0:0] foo;"
2015-01-15 12:53:12 +01:00
Clifford Wolf
8e8e791fb5
Consolidate "Blocking assignment to memory.." msgs for the same line
2015-01-15 12:41:52 +01:00
Fabio Utzig
fff6f00b3c
Enable bison to be customized
2015-01-08 09:56:20 -02:00
Clifford Wolf
1bd67d792e
Define YOSYS and SYNTHESIS in preproc
2015-01-02 17:11:54 +01:00
Clifford Wolf
eefe78be09
Fixed memory->start_offset handling
2015-01-01 12:56:01 +01:00
Clifford Wolf
0bb6b24c11
Added global yosys_celltypes
2014-12-29 14:30:33 +01:00
Clifford Wolf
90bc71dd90
dict/pool changes in ast
2014-12-29 03:11:50 +01:00
Clifford Wolf
137f35373f
Changed more code to dict<> and pool<>
2014-12-28 19:24:24 +01:00
Clifford Wolf
7751c491fb
Improved some warning messages
2014-12-27 03:40:27 +01:00
Clifford Wolf
12ca6538a4
Fixed mem2reg warning message
2014-12-27 03:26:30 +01:00
Clifford Wolf
a6c96b986b
Added Yosys::{dict,nodict,vector} container types
2014-12-26 10:53:21 +01:00
Clifford Wolf
edb3c9d0c4
Renamed extend() to extend_xx(), changed most users to extend_u0()
2014-12-24 09:51:17 +01:00
Clifford Wolf
1282a113da
Fixed supply0/supply1 with many wires
2014-12-11 13:56:20 +01:00
Clifford Wolf
76c83283c4
Fixed minor bug in parsing delays
2014-11-24 14:48:07 +01:00
Clifford Wolf
56c7d1e266
Fixed two minor bugs in constant parsing
2014-11-24 14:39:24 +01:00
Clifford Wolf
87333f3ae2
Added warning for use of 'z' constants in HDL
2014-11-14 19:59:50 +01:00
Clifford Wolf
4e5350b409
Fixed parsing of nested verilog concatenation and replicate
2014-11-12 19:10:35 +01:00
Clifford Wolf
fe829bdbdc
Added log_warning() API
2014-11-09 10:44:23 +01:00
Clifford Wolf
acf010d30d
Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions
2014-11-08 11:38:44 +01:00
Clifford Wolf
a21481b338
Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
2014-10-30 14:01:02 +01:00
Clifford Wolf
37aa2e02db
AST simplifier: optimize constant AST_CASE nodes before recursively descending
2014-10-29 08:29:51 +01:00
Clifford Wolf
f9c096eeda
Added support for task and function args in parentheses
2014-10-27 13:21:57 +01:00
Clifford Wolf
c4a2b3c1e9
Improvements in $readmem[bh] implementation
2014-10-26 23:29:36 +01:00
Clifford Wolf
70b2efdb05
Added support for $readmemh/$readmemb
2014-10-26 20:33:10 +01:00
Clifford Wolf
26cbe4a4e5
Fixed constant "cond ? string1 : string2" with strings of different size
2014-10-25 18:23:53 +02:00
Clifford Wolf
c5eb5e56b8
Re-introduced Yosys::readsome() helper function
...
(f.read() + f.gcount() made problems with lines > 16kB)
2014-10-23 10:58:36 +02:00
Clifford Wolf
750c615e7f
minor indenting corrections
2014-10-19 18:42:03 +02:00
Parviz Palangpour
de8adb8ec5
Builds on Mac 10.9.2 with LLVM 3.5.
2014-10-19 11:14:43 -05:00
Clifford Wolf
84ffe04075
Fixed various VS warnings
2014-10-18 15:20:38 +02:00
William Speirs
31267a1ae8
Header changes so it will compile on VS
2014-10-17 11:41:36 +02:00
William Speirs
fda52f05f2
Wrapped math in int constructor
2014-10-17 11:28:14 +02:00
Clifford Wolf
3838856a9e
Print "SystemVerilog" in "read_verilog -sv" log messages
2014-10-16 10:31:54 +02:00
Clifford Wolf
6b05a9e807
Fixed handling of invalid array access in mem2reg code
2014-10-16 00:44:23 +02:00
Clifford Wolf
f65e1c309f
Updated .gitignore file for ilang and verilog frontends
2014-10-15 01:14:38 +02:00
Clifford Wolf
c3e9922b5d
Replaced readsome() with read() and gcount()
2014-10-15 01:12:53 +02:00
William Speirs
fad0b0c506
Updated lexers & parsers to include prefixes
2014-10-15 00:48:19 +02:00
Clifford Wolf
0b9282a779
Added make_temp_{file,dir}() and remove_directory() APIs
2014-10-12 12:11:57 +02:00
Clifford Wolf
b1596bc0e7
Added run_command() api to replace system() and popen()
2014-10-12 10:57:15 +02:00
Clifford Wolf
35fbc0b35f
Do not the 'z' modifier in format string (another win32 fix)
2014-10-11 11:42:08 +02:00
Clifford Wolf
8263f6a74a
Fixed win32 troubles with f.readsome()
2014-10-11 11:36:22 +02:00
Clifford Wolf
0a651f112f
Disabled vhdl2verilog command for win32 builds
2014-10-11 10:46:19 +02:00
Clifford Wolf
bbd808072b
Added format __attribute__ to stringf()
2014-10-10 17:22:08 +02:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
48b00dccea
Another $clog2 bugfix
2014-09-08 12:25:23 +02:00
Clifford Wolf
680eaaac41
Fixed $clog2 (off by one error)
2014-09-06 19:31:04 +02:00
Clifford Wolf
deff416ea7
Fixed assignment of out-of bounds array element
2014-09-06 17:58:27 +02:00
Ruben Undheim
79cbf9067c
Corrected spelling mistakes found by lintian
2014-09-06 08:47:06 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
58367cd87a
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
2014-08-23 15:14:58 +02:00
Clifford Wolf
19cff41eb4
Changed frontend-api from FILE to std::istream
2014-08-23 15:03:55 +02:00
Clifford Wolf
98442e019d
Added emscripten (emcc) support to build system and some build fixes
2014-08-22 16:20:22 +02:00
Clifford Wolf
e218f0eacf
Added support for non-standard <plugin>:<c_name> DPI syntax
2014-08-22 14:30:29 +02:00
Clifford Wolf
74af3a2b70
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
2014-08-22 14:22:09 +02:00
Clifford Wolf
ad146c2582
Fixed small memory leak in ast simplify
2014-08-21 17:33:40 +02:00
Clifford Wolf
6c5cafcd8b
Added support for DPI function with different names in C and Verilog
2014-08-21 17:22:04 +02:00
Clifford Wolf
085c8e873d
Added AstNode::asInt()
2014-08-21 17:11:51 +02:00
Clifford Wolf
490d7a5bf2
Fixed memory leak in DPI function calls
2014-08-21 13:09:47 +02:00
Clifford Wolf
7bfc4ae120
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
Clifford Wolf
38addd4c67
Added support for global tasks and functions
2014-08-21 12:42:28 +02:00
Clifford Wolf
640d9fc551
Added "via_celltype" attribute on task/func
2014-08-18 14:29:30 +02:00
Clifford Wolf
acb435b6cf
Added const folding of AST_CASE to AST simplifier
2014-08-18 00:02:30 +02:00
Clifford Wolf
64713647a9
Improved AST ProcessGenerator performance
2014-08-17 02:17:49 +02:00
Clifford Wolf
d491fd8c19
Use stackmap<> in AST ProcessGenerator
2014-08-17 00:57:24 +02:00
Clifford Wolf
7f734ecc09
Added module->uniquify()
2014-08-16 23:50:36 +02:00
Clifford Wolf
83e2698e10
AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
2014-08-16 19:31:59 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
c7afbd9d8e
Fixed bug in "read_verilog -ignore_redef"
2014-08-15 01:53:22 +02:00
Clifford Wolf
978a933b6a
Added RTLIL::SigSpec::to_sigbit_map()
2014-08-14 23:14:47 +02:00
Clifford Wolf
c83b990458
Changed the AST genWidthRTLIL subst interface to use a std::map
2014-08-14 23:02:07 +02:00
Clifford Wolf
6d56172c0d
Fixed line numbers when using here-doc macros
2014-08-14 22:26:30 +02:00
Clifford Wolf
85e3cc12ac
Fixed handling of task outputs
2014-08-14 22:26:10 +02:00
Clifford Wolf
1bf7a18fec
Added module->ports
2014-08-14 16:22:52 +02:00
Clifford Wolf
f53984795d
Added support for non-standard """ macro bodies
2014-08-13 13:03:38 +02:00
Clifford Wolf
593264e9ed
Fixed building verific bindings
2014-08-12 15:21:06 +02:00
Clifford Wolf
2dc3333734
Also allow "module foobar(input foo, output bar, ...);" syntax
2014-08-07 16:41:27 +02:00
Clifford Wolf
d259abbda2
Added AST_MULTIRANGE (arrays with more than 1 dimension)
2014-08-06 15:52:54 +02:00
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
Clifford Wolf
0129d41efa
Fixed AST handling of variables declared inside a functions main block
2014-08-05 08:35:51 +02:00
Clifford Wolf
b5a3419ac2
Added support for non-standard "module mod_name(...);" syntax
2014-08-04 15:40:07 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
14412e6c95
Preparations for RTLIL::IdString redesign: cleanup of existing code
2014-08-02 00:45:25 +02:00
Clifford Wolf
bd74ed7da4
Replaced sha1 implementation
2014-08-01 19:01:10 +02:00
Clifford Wolf
c6fd82c70b
Fixed build of verific bindings
2014-07-31 16:45:23 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
7daad40ca4
Fixed counting verilog line numbers for "// synopsys translate_off" sections
2014-07-30 20:18:48 +02:00
Clifford Wolf
e605af8a49
Fixed Verilog pre-processor for files with no trailing newline
2014-07-29 20:14:25 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
48822e79a3
Removed left over debug code
2014-07-28 19:38:30 +02:00
Clifford Wolf
ec58965967
Fixed part selects of parameters
2014-07-28 19:24:28 +02:00
Clifford Wolf
a03297a7df
Set results of out-of-bounds static bit/part select to undef
2014-07-28 16:09:50 +02:00
Clifford Wolf
55521c085a
Fixed RTLIL code generator for part select of parameter
2014-07-28 15:31:19 +02:00
Clifford Wolf
0598bc8708
Fixed width detection for part selects
2014-07-28 15:19:34 +02:00
Clifford Wolf
27a872d1e7
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
Clifford Wolf
3c45277ee0
Added wire->upto flag for signals such as "wire [0:7] x;"
2014-07-28 12:12:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
ee65dea738
Fixed signdness detection of expressions with bit- and part-selects
2014-07-28 10:10:08 +02:00
Clifford Wolf
c4bdba78cb
Added proper Design->addModule interface
2014-07-27 21:12:09 +02:00
Clifford Wolf
7661ded8dd
Fixed verific bindings for new RTLIL api
2014-07-27 12:00:28 +02:00
Clifford Wolf
6b34215efd
Fixed ilang parser for new RTLIL API
2014-07-27 11:56:35 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
946ddff9ce
Changed a lot of code to the new RTLIL::Wire constructors
2014-07-26 20:12:50 +02:00
Clifford Wolf
97a59851a6
Added RTLIL::Cell::has(portname)
2014-07-26 16:11:28 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
...
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
309d64d46a
Fixed two memory leaks in ast simplify
2014-07-25 13:24:10 +02:00
Clifford Wolf
1488bc0c4f
Updated verific build/test instructions
2014-07-25 12:16:03 +02:00
Clifford Wolf
6aa792c864
Replaced more old SigChunk programming patterns
2014-07-24 23:10:58 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
375aa71dfe
Various fixes in Verific frontend for new RTLIL API
2014-07-23 21:35:01 +02:00
Clifford Wolf
20a7965f61
Various small fixes (from gcc compiler warnings)
2014-07-23 20:45:27 +02:00
Clifford Wolf
c094c53de8
Removed RTLIL::SigSpec::optimize()
2014-07-23 20:32:28 +02:00
Clifford Wolf
ec923652e2
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
2014-07-23 09:49:43 +02:00
Clifford Wolf
115dd959d9
SigSpec refactoring: More cleanups of old SigSpec use pattern
2014-07-22 23:50:21 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
7bffde6abd
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
2014-07-22 20:39:38 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
3b5f4ff39c
Fixed ilang parsing of process attributes
2014-07-22 20:39:37 +02:00
Clifford Wolf
d6d0e08834
Fixed make rules for ilang parser
2014-07-22 20:39:37 +02:00
Clifford Wolf
4147b55c23
Added "autoidx" statement to ilang file format
2014-07-21 15:15:18 +02:00
Clifford Wolf
361e0d62ff
Replaced depricated NEW_WIRE macro with module->addWire() calls
2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f
Removed deprecated module->new_wire()
2014-07-21 12:35:06 +02:00
Clifford Wolf
9b183539af
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
Clifford Wolf
5867f6bcdc
Added support for bit/part select to mem2reg rewriter
2014-07-17 13:49:32 +02:00
Clifford Wolf
6d69d4aaa8
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
Clifford Wolf
b171a4c1bc
Added "inout" ports support to read_liberty
2014-07-16 18:12:46 +02:00
Clifford Wolf
5057935722
Set blackbox attribute in "read_liberty -lib"
2014-07-16 18:12:16 +02:00
Clifford Wolf
24f58e57f3
Fixed spelling of "direction" in read_liberty messages
2014-07-16 18:02:28 +02:00
Clifford Wolf
543551b80a
changes in verilog frontend for new $mem/$memwr WR_EN interface
2014-07-16 12:49:50 +02:00
Clifford Wolf
0f9ca49dc6
Added passing of various options to vhdl2verilog
2014-07-12 10:02:39 +02:00
Clifford Wolf
55a1b8dbac
Fixed processing of initial values for block-local variables
2014-07-11 13:05:53 +02:00
Clifford Wolf
ee8ad72fd9
fixed parsing of constant with comment between size and value
2014-07-02 06:27:04 +02:00
Clifford Wolf
076182c34e
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
Clifford Wolf
4fc43d1932
More found_real-related fixes to AstNode::detectSignWidthWorker
2014-06-24 15:08:48 +02:00
Clifford Wolf
65b2e9c064
fixed signdness detection for expressions with reals
2014-06-21 21:41:13 +02:00
Clifford Wolf
80e4594695
Added AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:39:25 +02:00
Clifford Wolf
798ff88855
Improved handling of relational op of real values
2014-06-17 12:47:51 +02:00
Clifford Wolf
6c17d4f242
Improved ternary support for real values
2014-06-16 15:12:24 +02:00
Clifford Wolf
82bbd2f077
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
2014-06-16 15:05:37 +02:00
Clifford Wolf
0c4c79c4c6
Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)
2014-06-16 15:02:40 +02:00
Clifford Wolf
5bfe865cec
Added found_real feature to AstNode::detectSignWidth
2014-06-16 15:00:57 +02:00
Clifford Wolf
4d1df128fa
Improved AstNode::realAsConst for large numbers
2014-06-15 09:27:09 +02:00
Clifford Wolf
7f57bc8385
Improved parsing of large integer constants
2014-06-15 08:48:17 +02:00
Clifford Wolf
48dc6ab98d
Improved AstNode::asReal for large integers
2014-06-15 08:38:31 +02:00
Clifford Wolf
149fe83a8d
improved (fixed) conversion of real values to bit vectors
2014-06-14 21:00:51 +02:00
Clifford Wolf
d5765b5e14
Fixed relational operators for const real expressions
2014-06-14 19:33:58 +02:00
Clifford Wolf
f3b4a9dd24
Added support for math functions
2014-06-14 13:36:23 +02:00
Clifford Wolf
9bd7d5c468
Added handling of real-valued parameters/localparams
2014-06-14 12:00:47 +02:00
Clifford Wolf
fc7b6d172a
Implemented more real arithmetic
2014-06-14 11:27:05 +02:00
Clifford Wolf
442a8e2875
Implemented basic real arithmetic
2014-06-14 08:51:22 +02:00
Clifford Wolf
9dd16fa41c
Added real->int convertion in ast genrtlil
2014-06-14 07:44:19 +02:00
Clifford Wolf
7ef0da32cd
Added Verilog lexer and parser support for real values
2014-06-13 11:29:23 +02:00
Clifford Wolf
482d9208aa
Added read_verilog -sv options, added support for bit, logic,
...
allways_ff, always_comb, and always_latch
2014-06-12 11:54:20 +02:00
Clifford Wolf
e275e8eef9
Add support for cell arrays
2014-06-07 11:48:50 +02:00
Clifford Wolf
0b1ce63a19
Added support for repeat stmt in const functions
2014-06-07 10:47:53 +02:00
Clifford Wolf
7c8a7b2131
further improved const function support
2014-06-07 00:02:05 +02:00
Clifford Wolf
5281562d0e
made the generate..endgenrate keywords optional
2014-06-06 23:05:01 +02:00
Clifford Wolf
76da2fe172
improved const function support
2014-06-06 22:55:02 +02:00
Clifford Wolf
5c10d2ee36
fix functions with no block (but single statement, loop, etc.)
2014-06-06 21:29:23 +02:00
Clifford Wolf
ab54ce17c8
improved ast simplify of const functions
2014-06-06 17:40:45 +02:00
Clifford Wolf
b5cd7a0179
added while and repeat support to verilog parser
2014-06-06 17:40:04 +02:00
Clifford Wolf
f9c1cd5edb
Improved error message for options after front-end filename arguments
2014-06-04 09:10:50 +02:00
Johann Glaser
63dfbb18cf
new flags -ignore_miss_func and -ignore_miss_dir for read_liberty
2014-05-28 16:50:13 +02:00
Clifford Wolf
7188542155
Fixed clang -Wdeprecated-register warnings
2014-04-20 14:28:23 +02:00
Clifford Wolf
a1be4816d6
Replaced depricated %name-prefix= bison directive
2014-04-20 14:22:11 +02:00
Clifford Wolf
a3b9692a68
Fixed mapping of Verific WIDE_DFFRS operator
2014-03-20 13:40:01 +01:00
Clifford Wolf
470c2455e4
Fixed mapping of Verific FADD primitive with unconnected outputs
2014-03-20 13:26:52 +01:00
Clifford Wolf
cdf1257565
Progress in Verific bindings
2014-03-17 14:43:16 +01:00
Clifford Wolf
0b0dcfda7d
Progress in Verific bindings
2014-03-17 02:43:53 +01:00
Clifford Wolf
a67cd2d4a2
Progress in Verific bindings
2014-03-17 01:56:00 +01:00
Clifford Wolf
acda74c12c
Added support for memories to verific bindings
2014-03-16 17:05:05 +01:00
Clifford Wolf
7545510edc
Use Verific Net::{IsGnd,IsPwr} API in Verific bindings
2014-03-16 16:06:03 +01:00