Commit Graph

1442 Commits

Author SHA1 Message Date
N. Engelhardt 0fc5812dcd
Merge pull request #4541 from YosysHQ/krys/compiler-warnings
Resolve (some) compiler warnings
2024-08-26 15:04:16 +02:00
Emil J. Tywoniak 4847caac49 driver: print maximum memory usage on macOS as well 2024-08-19 12:50:12 +02:00
Krystine Sherwin 7b47f645d7
Address warnings
- Setting default values
- Fixing mismatched types
- Guarding unused var
2024-08-16 04:30:31 +12:00
Emil J 92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy
cost: add keep_hierarchy pass with min_cost argument
2024-07-29 16:33:08 +02:00
Emil J 051d83205d
Merge pull request #4471 from georgerennie/hashlib_primes
hashlib: Add some more primes
2024-07-29 15:10:22 +02:00
Emil J. Tywoniak 4b29f64142 cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter 2024-07-29 10:26:02 +02:00
Emil J 49eaa108a5
Merge pull request #4425 from YosysHQ/emil/doc-sigmap
sigmap: comments
2024-07-29 10:18:44 +02:00
Roland Coeurjoly ce11ddbf21 Simplified run_frontend by using a lambda function for file extension checks and combining blif and eblif into a single condition. 2024-07-23 17:55:04 +02:00
Roland Coeurjoly 8c1431f373 Guess VHDL frontend for both *.vhd and *vhdl files 2024-07-23 17:01:57 +02:00
Emil J. Tywoniak 583db7b15e sigmap: comments 2024-07-18 16:02:11 +02:00
Alexander von Gluck 2f514487cb haiku: Basic fixes to build under Haiku 2024-07-15 12:57:34 +02:00
George Rennie 339d4e8932 hashlib: Correct prime sequence 2024-07-02 08:10:18 +01:00
George Rennie 78ae4ed9ac hashlib: Add some more primes
* Add some primes as suggested in #4458. This allows larger hashtables
  to be allocated for very big designs
2024-07-01 12:37:41 +01:00
Martin Povišer 07daf61ae6
Merge pull request #4467 from povik/fix-add-shiftx
rtlil: Fix `addShiftx` for signed shifts
2024-06-26 18:17:28 +02:00
Martin Povišer 89d939334e rtlil: Fix `addShiftx` for signed shifts
Only the `B` input (the shift amount) can be marked as signed on a
`$shiftx` cell. Adapt the helper accordingly and prevent it from
creating invalid RTLIL when called with `is_signed` set. Previously
it would mark both `A` and `B` as signed.
2024-06-21 15:14:08 +02:00
Miodrag Milanovic 141a2e3638 Make C++17 compiler required 2024-06-17 16:55:36 +02:00
Martin Povišer fc82251105 techmap: Support dynamic cell types 2024-05-03 13:33:28 +02:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup
Typo fixing
2024-04-25 09:54:48 +12:00
Martin Povišer 178eceb32d rtlil: Replace the packed `SigSpec::extract` impl 2024-04-22 16:23:51 +02:00
Jannis Harder 0d30a4d479 rtlil: Add packed `extract` implementation for `SigSpec`
Previously `extract` on a `SigSpec` would always unpack it. Since a
significant amount of `SigSpec`s have one or few chunks, it's worth
having a dedicated implementation.

This is especially true, since the RTLIL frontend calls into this for
every `wire [lhs:rhs]` slice, making this `extract` take up 40% when
profiling `read_rtlil` with one of the largest coarse grained RTLIL
designs I had on hand.

With this change the `read_rtlil` profile looks like I would expect it
to look like, but I noticed that a lot of the other core RTLIL methods
also are a bit too eager with unpacking or implementing
`SigChunk`/`Const` overloads that just convert to a single chunk
`SigSpec` and forward to the implementation for that, when a direct
implementation would avoid temporary std::vector allocations. While not
relevant for `read_rtlil`, to me it looks like there might be a few easy
overall performance gains to be had by addressing this more generally.
2024-04-22 13:26:17 +02:00
Jannis Harder d8687e87b1 kernel: Avoid including files outside include guards
This adjusts the way the headers kernel/{yosys,rtlil,register,log}.h
include each other to avoid the need of including headers outside of
include guards as well as avoiding the inclusion of rtlil.h in the
middle of yosys.h with rtlil.h depending on the prefix of yosys.h, and
the suffix of yosys.h depending on rtlil.h.

To do this I moved some of the declaration in yosys.h into a new header
yosys_common.h. I'm not sure if that is strictly necessary.

Including any of these files still results in the declarations of all
these headers being included, so this shouldn't be a breaking change for
any passes or external plugins.

My main motivation for this is that ccls's (clang based language server)
include guard handling gets confused by the previous way the includes
were done. It often ends up treating the include guard as a generic
disabled preprocessor conditional, breaking navigation and highlighting
for the core RTLIL data structures.

Additionally I think avoiding cyclic includes in the middle of header
files that depend on includes being outside of include guards will also
be less confusing for developers reading the code, not only for tools
like ccls.
2024-04-02 16:53:56 +02:00
Catherine 94170388a9 fmt: if enabled, group padding zeroes.
Before this commit, the combination of `_` and `0` format characters
would produce a result like `000000001010_1010`.
After this commit, it would be `0000_0000_1010_1010`.

This has a slight quirk where a format like `{:020_b}` results in
the output `0_0000_0000_1010_1010`, which is one character longer than
requested. Python has the same behavior, and it's not clear what would
be strictly speaking correct, so Python behavior is implemented.
2024-04-02 12:13:22 +02:00
Catherine 27cb4c52b4 fmt: allow padding characters other than `'0'` and `' '`.
When converted to Verilog, padding characters are replaced with one of
these two. Otherwise padding is performed with exactly that character.
2024-04-02 12:13:22 +02:00
Catherine ddf7b46955 fmt,cxxrtl: fix printing of non-decimal signed numbers.
Also fix interaction of `NUMERIC` justification with `show_base`.
2024-04-02 12:13:22 +02:00
Catherine 00c5b60dfd fmt,cxxrtl: add option to group digits in numbers.
The option is serialized to RTLIL as `_` (to match Python's option with
the same symbol), and sets the `group` flag. This flag inserts an `_`
symbol between each group of 3 digits (for decimal) or four digits (for
binary, hex, and octal).
2024-04-02 12:13:22 +02:00
Catherine 7b94599162 fmt,cxxrtl: add option to print numeric base (`0x`, etc).
The option is serialized to RTLIL as `#` (to match Python's and Rust's
option with the same symbol), and sets the `show_base` flag. Because
the flag is called `show_base` and not e.g. `alternate_format` (which
is what Python and Rust call it), in addition to the prefixes `0x`,
`0X`, `0o`, `0b`, the RTLIL option also prints the `0d` prefix.
2024-04-02 12:13:22 +02:00
Catherine bf5a960668 fmt,cxxrtl: add `UNICHAR` format type.
This format type is used to print an Unicode character (code point) as
its UTF-8 serialization. To this end, two UTF-8 decoders (one for fmt,
one for cxxrtl) are added for rendering. When converted to a Verilog
format specifier, `UNICHAR` degrades to `%c` with the low 7 bits of
the code point, which has equivalent behavior for inputs not exceeding
ASCII. (SystemVerilog leaves source and display encodings completely
undefined.)
2024-04-02 12:13:22 +02:00
Catherine 1780e2eb1e fmt,cxxrtl: add support for `NUMERIC` justification.
Before this commit, the existing alignments were `LEFT` and `RIGHT`,
which added the `padding` character to the right and left just before
finishing formatting. However, if `padding == '0'` and the alignment is
to the right, then the padding character (digit zero) was added after
the sign, if one is present.

After this commit, the special case for `padding == '0'` is removed,
and the new justification `NUMERIC` adds the padding character like
the justification `RIGHT`, except after the sign, if one is present.
(Space, for the `SPACE_MINUS` sign mode, counts as the sign.)
2024-04-02 12:13:22 +02:00
Catherine 6d6b138607 fmt,cxxrtl: support `{,PLUS_,SPACE_}MINUS` integer formats.
The first two were already supported with the `plus` boolean flag.
The third one is a new specifier, which is allocated the ` ` character.
In addition, `MINUS` is now allocated the `-` character, but old format
where there is no `+`, `-`, or `-` in the respective position is also
accepted for compatibility.
2024-04-02 12:13:22 +02:00
Catherine 8388846e3a fmt,cxxrtl: add support for uppercase hex format.
This is necessary for translating Python format strings in Amaranth.
2024-04-02 12:13:22 +02:00
Catherine a5441bc00c fmt: `FmtPart::{STRING→LITERAL},{CHARACTER→STRING}`.
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
2024-04-02 12:13:22 +02:00
N. Engelhardt c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges
Use cell edges data in `check`, improve messages
2024-03-25 16:19:35 +01:00
Krystine Sherwin 3eeefd23e3
Typo fixup(s) 2024-03-18 11:09:23 +13:00
Krystine Sherwin d2bf5a83af
Merge branch 'origin/master' into krys/docs 2024-03-18 10:39:30 +13:00
Miodrag Milanovic 5e05300e7b fix compile warning 2024-03-11 10:55:09 +01:00
Martin Povišer d01728aaa5 celledges: Register async FF paths 2024-03-11 10:45:36 +01:00
Martin Povišer 87e72ef86f celledges: Add read ports arst paths 2024-03-11 10:45:17 +01:00
Martin Povišer 4a10e78777 celledges: Emit empty edges for write/init ports 2024-03-11 10:45:17 +01:00
Martin Povišer 3a1ef44564 celledges: Describe asynchronous read ports 2024-03-11 10:45:17 +01:00
Martin Povišer 6e5f40e364 utils: Save detected loops with their nodes in-order 2024-03-11 10:43:49 +01:00
N. Engelhardt d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
celledges: support shift ops
2024-03-08 09:35:47 +01:00
Krystine Sherwin 1455941ab9
Merge branch 'master' into krys/docs 2024-03-05 05:48:46 +13:00
Jason Thorpe a02d4e7853 Tweak the FreeBSD version of proc_self_dirname() to work on NetBSD use it. 2024-03-03 07:54:39 -08:00
Martin Povišer dd11a5a37c Shrink further 2024-02-26 16:25:46 +01:00
Martin Povišer b5b737de38 Shrink a bit more 2024-02-22 22:20:35 +01:00
Martin Povišer f7737a12ca Cut down startup banner 2024-02-22 22:14:32 +01:00
Martin Povišer 173f4b5fbd Bump Claire's notices 2024-02-22 22:03:44 +01:00
Martin Povišer f5013d035e rtlil: Fix `Const` hashing omission 2024-02-19 15:45:54 +01:00
Jannis Harder 3473b6dd27
Merge pull request #4206 from povik/cli-crashes
driver: Fix crashes on missing cli arguments
2024-02-12 16:39:38 +01:00
Martin Povišer 54a97f8bb7 driver: Fix crashes on missing cli arguments 2024-02-12 14:56:23 +01:00