riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,868 Commits 89 Branches 49 Tags 38 MiB
Commit Graph

7868 Commits

Author SHA1 Message Date
Eddie Hung 53ea5daa42 Call 'wreduce' after mul2dsp to avoid unextend() 2019-09-25 14:04:36 -07:00
Eddie Hung 93363c94a2 Oops. Actually use __NAME__ in ABC_DSP48E1 macro 2019-09-25 10:33:16 -07:00
SergeyDegtyar b66364ada2 Change sync controls to async. 2019-09-25 14:43:26 +03:00
Clifford Wolf 739c621330
Merge pull request #1402 from YosysHQ/clifford/portlist 
Add "portlist" command
 2019-09-25 09:20:54 +02:00
Clifford Wolf b432c9b44b Improve "portlist" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-25 09:20:38 +02:00
Clifford Wolf 6c427d36dd Add "portlist" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-24 18:08:59 +02:00
SergeyDegtyar fc6ebf8268 adffs test update (equiv_opt -multiclock). 2019-09-24 14:55:32 +03:00
Eddie Hung b41d2fb4e4 Add (* techmap_autopurge *) to abc_unmap.v too 2019-09-23 22:02:22 -07:00
Eddie Hung 44374b1b2b "abc_padding" attr for blackbox outputs that were padded, remove them later 2019-09-23 21:58:40 -07:00
Eddie Hung c340fbfab2 Force $inout.out ports to begin with '$' to indicate internal 2019-09-23 21:58:04 -07:00
Eddie Hung 11ac37733d Add techmap_autopurge to outputs in abc_map.v too 2019-09-23 21:56:28 -07:00
Eddie Hung 27167848f4 Revert "Add a xilinx_finalise pass" 
This reverts commit 23d90e0439.
 2019-09-23 19:52:55 -07:00
Eddie Hung 0f53893104 Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" 
This reverts commit 67c2db3486.
 2019-09-23 19:52:55 -07:00
Eddie Hung 29db96fa1f Revert "Vivado does not like zero width port connections" 
This reverts commit 895e2befa7.
 2019-09-23 19:52:54 -07:00
Eddie Hung 895e2befa7 Vivado does not like zero width port connections 2019-09-23 19:04:07 -07:00
Eddie Hung 67c2db3486 Remove (* techmap_autopurge *) from abc_unmap.v since no effect 2019-09-23 18:56:18 -07:00
Eddie Hung 23d90e0439 Add a xilinx_finalise pass 2019-09-23 18:56:02 -07:00
Eddie Hung e556d48d45 Set [AB]CASCREG to legal values 2019-09-23 16:00:11 -07:00
Eddie Hung b824a56cde Comment to explain separating CREG packing 2019-09-23 13:58:10 -07:00
Eddie Hung 15dfbc8125 Separate out CREG packing into new pattern, to avoid conflict with PREG 2019-09-23 13:27:10 -07:00
Eddie Hung 26a6c55665 Move log_debug("\n") later 2019-09-23 13:27:00 -07:00
Eddie Hung d0dbbc2605 Move unextend initialisation later 2019-09-23 13:26:34 -07:00
Eddie Hung a67af3d5e5 Use new port() overload once more 2019-09-23 13:00:44 -07:00
Miodrag Milanović 057dae4f78
Merge pull request #1399 from nakengelhardt/fix-show-macos 
fix show command for macos
 2019-09-23 20:06:40 +02:00
Eddie Hung bcee87a457 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-23 10:58:28 -07:00
N. Engelhardt 2b81ce5648 add xdot dependency to Brewfile 2019-09-23 18:25:04 +02:00
N. Engelhardt 3bed4cb18a fix show command for macos 2019-09-23 17:47:05 +02:00
SergeyDegtyar 1070f2e90b Add new tests for Efinix architecture. 
Problems/questions:
	- fsm.ys. equiv_opt -assert failed because of unproven cells;
	- latches.ys,tribuf.ys - internal cells present;
	- memory.ys - sat called with -verify and proof did fail.
 2019-09-23 15:51:41 +03:00
Benedikt Tutzer f39269805d Generate Python wrappers for inline constructors 
Fixes: #1353
 2019-09-23 13:17:59 +02:00
SergeyDegtyar 27377c4663 Add new tests for Anlogic architecture 
Problems/questions:
	- memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type
EG_LOGIC_DRAM16X4) to SAT database.
		Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM?
	- Internal cell type $_TBUF_  is present.
 2019-09-23 12:12:02 +03:00
whitequark 4f426c2ac4 write_verilog: do not print (*init*) attributes on regs. 
If an init value is emitted for a reg, an (*init*) attribute is never
necessary, since it is exactly equivalent. On the other hand, some
tools that consume Verilog (ISE, Vivado, Quartus) complain about
(*init*) attributes because their interpretation differs from Yosys.

All (*init*) attributes that would not become reg init values anyway
are emitted as before.
 2019-09-22 16:52:06 +00:00
Clifford Wolf 0a2d8db793
Merge pull request #1392 from YosysHQ/eddie/fix1391 
(* techmap_autopurge *) fixes when ports aren't consistently-sized
 2019-09-21 11:25:36 +02:00
Eddie Hung 7c8de1dd18 Hell let's add the original #1381 testcase too 2019-09-20 17:58:51 -07:00
Eddie Hung ec08a031b5 Revert abc9.cc 2019-09-20 17:52:23 -07:00
Eddie Hung 6258e6a7e2 Add testcase 2019-09-20 17:51:45 -07:00
Eddie Hung 72ce06909e Trim mismatched connection to be same (smallest) size 2019-09-20 17:51:36 -07:00
Eddie Hung 567e5f0aa7 Fix first testcase in #1391 2019-09-20 17:51:27 -07:00
Eddie Hung 4401e5f142 Grammar 2019-09-20 14:24:31 -07:00
Eddie Hung 53817b8575 Use new port/param overload in pmg 2019-09-20 14:21:22 -07:00
Eddie Hung d122083a11 Output pattern matcher items as log_debug() 2019-09-20 12:42:28 -07:00
Eddie Hung 95644b00cb OPMODE is port not param 2019-09-20 12:37:29 -07:00
Eddie Hung 3fb839e255 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-20 12:21:36 -07:00
Eddie Hung eb597431f0 Do not run xilinx_dsp_cascadeAB for now 2019-09-20 12:18:37 -07:00
Eddie Hung 0bca366bcd WIP for xiinx_dsp_cascadeAB 2019-09-20 12:07:14 -07:00
Eddie Hung b0ad2592be Run until convergence 2019-09-20 12:04:16 -07:00
Eddie Hung 1b892ca1be Cleanup ice40_dsp.pmg 2019-09-20 12:03:45 -07:00
Eddie Hung d88903e610 Cleanup xilinx_dsp 2019-09-20 12:03:25 -07:00
Eddie Hung 1809f463fb More exceptions 2019-09-20 12:03:10 -07:00
Eddie Hung ab46d9017b Fix signedness bug 2019-09-20 10:11:36 -07:00
Eddie Hung 70c5444b25 Update doc 2019-09-20 10:07:54 -07:00