riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
13,642 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Catherine d9a4a42389 write_verilog: don't `assign` to a `reg`. 
Fixes #2035.
 2024-04-03 13:06:45 +02:00