Commit Graph

9 Commits

Author SHA1 Message Date
Lofty 8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
Miodrag Milanovic e6f7cf3b29 Update tests 2023-06-09 14:41:45 +02:00
gatecat eb106732d9 intel_alm: Add global buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
gatecat 5dba138c87 intel_alm: Add IO buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 22:37:06 +01:00
Marcelina Kościelnicka 50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path.
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
2020-08-20 12:44:09 +02:00
Dan Ravensloft 62311b7ec0 intel_alm: increase abc9 -W 2020-07-26 23:56:54 +02:00
Dan Ravensloft 4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Dan Ravensloft 0d4c2f0a65 intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00