Clifford Wolf
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58367cd87a
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Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
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2014-08-23 15:14:58 +02:00 |
Clifford Wolf
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19cff41eb4
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Changed frontend-api from FILE to std::istream
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2014-08-23 15:03:55 +02:00 |
Clifford Wolf
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5dce303a2a
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Changed backend-api from FILE to std::ostream
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2014-08-23 13:54:21 +02:00 |
Clifford Wolf
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fff12c719f
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Added "stat -width"
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2014-08-22 17:20:28 +02:00 |
Clifford Wolf
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98442e019d
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Added emscripten (emcc) support to build system and some build fixes
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2014-08-22 16:20:22 +02:00 |
Clifford Wolf
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ba83a7bdc6
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Added DPI-C documentation to README file
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2014-08-22 14:37:14 +02:00 |
Clifford Wolf
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e218f0eacf
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Added support for non-standard <plugin>:<c_name> DPI syntax
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2014-08-22 14:30:29 +02:00 |
Clifford Wolf
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74af3a2b70
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Archibald Rust and Clifford Wolf: ffi-based dpi_call()
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2014-08-22 14:22:09 +02:00 |
Clifford Wolf
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a3494fa9ed
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Added "plugin" command
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2014-08-22 14:00:11 +02:00 |
Clifford Wolf
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752650a062
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Updated ABC to 4d547a5e065b
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2014-08-22 12:20:23 +02:00 |
Clifford Wolf
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c2df5b9175
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Cosmetic changes to FSM tests
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2014-08-21 17:40:49 +02:00 |
Clifford Wolf
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ad146c2582
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Fixed small memory leak in ast simplify
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2014-08-21 17:33:40 +02:00 |
Clifford Wolf
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6c5cafcd8b
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Added support for DPI function with different names in C and Verilog
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2014-08-21 17:22:04 +02:00 |
Clifford Wolf
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085c8e873d
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Added AstNode::asInt()
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2014-08-21 17:11:51 +02:00 |
Clifford Wolf
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490d7a5bf2
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Fixed memory leak in DPI function calls
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2014-08-21 13:09:47 +02:00 |
Clifford Wolf
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4f35a81ad9
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Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-08-21 12:58:16 +02:00 |
Clifford Wolf
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7bfc4ae120
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Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
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2014-08-21 12:43:51 +02:00 |
Clifford Wolf
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38addd4c67
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Added support for global tasks and functions
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2014-08-21 12:42:28 +02:00 |
Clifford Wolf
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b37d70dfd7
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Added mod->addGate() methods for new gate types
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2014-08-19 14:26:54 +02:00 |
Clifford Wolf
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a92a68ce52
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Using "via_celltype" in $mul carry-save-acc implementation
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2014-08-18 14:30:20 +02:00 |
Clifford Wolf
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640d9fc551
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Added "via_celltype" attribute on task/func
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2014-08-18 14:29:30 +02:00 |
Clifford Wolf
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6f33fc3e87
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Performance fix for new $__lcu techmap rule
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2014-08-18 00:27:54 +02:00 |
Clifford Wolf
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4b3834e0cc
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Replaced recursive lcu scheme with bk adder
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2014-08-18 00:03:33 +02:00 |
Clifford Wolf
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acb435b6cf
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Added const folding of AST_CASE to AST simplifier
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2014-08-18 00:02:30 +02:00 |
Clifford Wolf
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aa7a3ed83f
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Fixed proc_{self,share}_dirname error handling
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2014-08-17 02:25:59 +02:00 |
Clifford Wolf
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aa3a6663e2
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Makefile fixes
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2014-08-17 02:24:53 +02:00 |
Clifford Wolf
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64713647a9
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Improved AST ProcessGenerator performance
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2014-08-17 02:17:49 +02:00 |
Clifford Wolf
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f3326a6421
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Improved sig.remove2() performance
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2014-08-17 02:16:56 +02:00 |
Clifford Wolf
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d491fd8c19
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Use stackmap<> in AST ProcessGenerator
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2014-08-17 00:57:24 +02:00 |
Clifford Wolf
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9bacc0b54c
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Added stackmap<> container
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2014-08-17 00:56:47 +02:00 |
Clifford Wolf
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410d043dd8
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Renamed toposort.h to utils.h
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2014-08-17 00:55:35 +02:00 |
Clifford Wolf
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7f734ecc09
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Added module->uniquify()
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2014-08-16 23:50:36 +02:00 |
Clifford Wolf
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f82c978e08
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Fixed AOI/OAI expr handling in verilog backend
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2014-08-16 22:05:09 +02:00 |
Clifford Wolf
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976bda7102
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Multiply using a carry-save accumulator
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2014-08-16 21:07:29 +02:00 |
Clifford Wolf
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3b9157f9a6
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Added "test_cell -s <seed>"
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2014-08-16 19:44:31 +02:00 |
Clifford Wolf
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83e2698e10
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AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
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2014-08-16 19:31:59 +02:00 |
Clifford Wolf
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47c2637a96
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
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2014-08-16 18:29:39 +02:00 |
Clifford Wolf
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56a30cf42c
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Added CellTypes::cell_evaluable()
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2014-08-16 16:17:07 +02:00 |
Clifford Wolf
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1ddf150c35
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Changes in techmap $__alu interface
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2014-08-16 16:01:58 +02:00 |
Clifford Wolf
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eb17fbade5
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Added "opt -fast"
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2014-08-16 15:34:15 +02:00 |
Clifford Wolf
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dbdf89c705
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Added log_spacer()
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2014-08-16 15:34:00 +02:00 |
Clifford Wolf
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674f421b47
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Bugfix in iopadmap
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2014-08-15 14:29:42 +02:00 |
Clifford Wolf
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b64b38eea2
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Renamed $lut ports to follow A-Y naming scheme
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2014-08-15 14:18:40 +02:00 |
Clifford Wolf
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f092b50148
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Renamed $_INV_ cell type to $_NOT_
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2014-08-15 14:11:40 +02:00 |
Clifford Wolf
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bf486002d9
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Removed old doc references to $safe_pmux
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2014-08-15 14:04:35 +02:00 |
Clifford Wolf
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ca87116449
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More idstring sort_by_* helpers and fixed tpl ordering in techmap
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2014-08-15 02:40:46 +02:00 |
Clifford Wolf
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8ff71b5ae5
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Added Frontend "+/" filename syntax for files from proc_share_dir
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2014-08-15 02:08:02 +02:00 |
Clifford Wolf
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d320e75087
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document "techmap -map %<design-name>"
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2014-08-15 02:01:30 +02:00 |
Clifford Wolf
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c7afbd9d8e
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Fixed bug in "read_verilog -ignore_redef"
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2014-08-15 01:53:22 +02:00 |
Clifford Wolf
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978a933b6a
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Added RTLIL::SigSpec::to_sigbit_map()
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2014-08-14 23:14:47 +02:00 |