yosys

Commit Graph

Author	SHA1	Message	Date
Krystine Sherwin	3e653fe4a6	docs: more on wreduce in synth starter	2024-01-04 12:49:48 +13:00
Krystine Sherwin	9f1c445fbf	docs: work on example_synth Split hardware mapping from `fifo.ys` into `fifo_map.ys`. Reduces size of `fifo.out` log and allows separate yosys calls in the makefile. Some tidy up and minor changes in `fifo.ys` for better discussion. Filled out note on `clean` (changed from `opt_clean`) and introduced `;;`. Highlighted `$memrd` and added a paragraph about it. More detail on the flatten and merging of `fifo_reader` block. Brief discussion on the changes from `$memrd` to `$memrd_v2`.	2024-01-03 11:47:33 +13:00
Krystine Sherwin	50d8c1b258	First pass example_synth done Split coarse grain representation into 4 parts, loosely: fsm/opt, other optimizations/techmap/memory_dff, DSPs, alumacc/memory -nomap. Split hardware mapping into subsections as well: memory blocks (map_ram and map_ffram), arithmetic (map_gates), FFs (map_ffs), LUTs (map_luts and briefly abc), and other (map_cells and a note on hilomap and iopadmap). Also add `-T` flag to Yosys call to remove footer from log output.	2023-12-20 14:08:06 +13:00
Krystine Sherwin	a33b1b6059	More work on example_synth Added highlighting in (most) schematics. Written down to end of coarse-grain, with a couple of TODOs for filling in gaps. Includes `techmap_synth.rst` stub.	2023-12-18 17:49:15 +13:00
Krystine Sherwin	742ec78ca3	Switching example synth to fifo Fifo code based on SBY quick start. Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.	2023-12-18 13:19:01 +13:00

5 Commits