4 Commits

Author	SHA1	Message	Date
Marcin Kościelnicki	aff6ad1ce0	xilinx: Improve flip-flop handling. ... This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.	2019-12-18 13:43:43 +01:00
Marcin Kościelnicki	7562e7304e	xilinx: Use INV instead of LUT1 when applicable	2019-11-25 20:40:39 +01:00
Miodrag Milanovic	5603595e5c	Share common tests	2019-10-18 12:19:59 +02:00
Miodrag Milanovic	c2ec7ca703	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00