Patrick Urban
0a72952d5f
synth_gatemate: Apply review remarks
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* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
2021-11-13 21:53:25 +01:00
github-actions[bot]
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2021-11-13 00:52:01 +00:00
Miodrag Milanovic
48a628522b
update abc
2021-11-12 12:40:24 +01:00
Miodrag Milanovic
b4f68e3cca
Update abc
2021-11-12 09:00:32 +01:00
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2021-11-11 00:54:18 +00:00
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2021-11-10 00:54:39 +00:00
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2021-11-07 00:54:38 +00:00
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2021-11-06 00:51:08 +00:00
Miodrag Milanovic
a28ee81be0
Next dev cycle
2021-11-05 12:52:24 +01:00
Miodrag Milanovic
360fed8e4d
Release version 0.11
2021-11-05 12:47:38 +01:00
Miodrag Milanović
5a5244a12e
Merge pull request #3067 from YosysHQ/aki/ci_update
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Update the Linux and macOS CI jobs
2021-11-05 09:58:35 +01:00
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2021-11-03 00:52:24 +00:00
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2021-11-02 00:56:31 +00:00
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2021-11-01 01:05:04 +00:00
Aki Van Ness
ad81cff823
Changed the Makefile to have an explicit `CXXSTD` parameter which allows for the setting of other C++ standards, the default is `c++11`
2021-10-31 20:07:30 -04:00
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2021-10-30 00:51:07 +00:00
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2021-10-28 00:52:35 +00:00
Miodrag Milanovic
32673edfea
Revert "Compile option for enabling async load verific support"
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This reverts commit b8624ad2ae
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2021-10-27 15:55:43 +02:00
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2021-10-27 00:51:44 +00:00
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2021-10-26 00:51:59 +00:00
Miodrag Milanovic
b8624ad2ae
Compile option for enabling async load verific support
2021-10-25 09:04:43 +02:00
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52ba31b1c0
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2021-10-22 01:00:39 +00:00
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2021-10-21 00:59:29 +00:00
Miodrag Milanovic
bf79ff5927
If verific have vhdl lib it is required by other libs
2021-10-20 13:08:08 +02:00
Miodrag Milanovic
150ce305f9
Forgot to remove from main list
2021-10-20 12:37:22 +02:00
Miodrag Milanovic
17269ae59b
Option to disable verific VHDL support
2021-10-20 10:02:58 +02:00
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2021-10-20 00:56:49 +00:00
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2021-10-09 00:51:28 +00:00
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2021-10-08 00:57:28 +00:00
Marcelina Kościelnicka
4e70c30775
FfData: some refactoring.
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- FfData now keeps track of the module and underlying cell, if any (so
calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
compilation
- the "flip FF data sense by inserting inverters in front and after"
functionality that zinit uses is moved onto FfData class and beefed up
to have dffsr support, to support more use cases
2021-10-07 04:24:06 +02:00
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2021-09-28 00:53:49 +00:00
Miodrag Milanovic
070cad5f4b
Prepare for next release cycle
2021-09-27 16:24:43 +02:00
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