yosys

mirror of https://github.com/YosysHQ/yosys.git

Author	SHA1	Message	Date
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Marcelina Kościelnicka	93508d58da	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
Marcelina Kościelnicka	0aad88a2fb	Add clean_zerowidth pass, use it for Verilog output. This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.	2021-12-12 19:56:50 +01:00