riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,777 Commits 81 Branches 48 Tags 63 MiB
Commit Graph

3777 Commits

Author SHA1 Message Date
Clifford Wolf e45d1c8865 Tiny fixes to verilog parser 2013-03-23 18:54:31 +01:00
Clifford Wolf bee57c808a Various improvements in intersynth backend 2013-03-23 12:02:09 +01:00
Clifford Wolf 80aefb3eaa Added intersynth backend 2013-03-23 10:58:14 +01:00
Clifford Wolf 47325fb271 Added help -write-tex-command-reference-manual option 2013-03-21 11:33:56 +01:00
Clifford Wolf 69ce1191c0 Added eclipse CDT project files to .gitignore 2013-03-21 10:59:35 +01:00
Clifford Wolf 8f610dca58 Added -S option for simple synthesis to gate logic 2013-03-21 09:52:21 +01:00
Clifford Wolf 87c7717566 Avoid verilog-2k in verilog backend 2013-03-21 09:51:25 +01:00
Clifford Wolf 91b94ef57b Disabled the per-default dumping of ILANG code 2013-03-21 09:12:32 +01:00
Clifford Wolf 8d37d1e08b Added -nomap option to memory pass 2013-03-21 09:11:06 +01:00
Clifford Wolf 0d39366e2c Merge branch 'hansiglaser-master' 2013-03-19 13:47:46 +01:00
Clifford Wolf 9f10acb840 added optimizations for single-bit $eq/$ne with constant input to opt_const 2013-03-19 13:33:33 +01:00
Clifford Wolf d8a7fa6b67 improved $mux optimization in opt_const 2013-03-19 13:32:39 +01:00
Clifford Wolf b7fcf1fb9a keep $mux and $_MUX_ optimizations separate in opt_const 2013-03-19 13:32:04 +01:00
Johann Glaser 1d30c66a7f added a TODO 2013-03-18 22:06:53 +01:00
Johann Glaser 69674652c5 added one more suggestion to optimize MUXes in pass "opt_const" 2013-03-18 22:06:16 +01:00
Johann Glaser a4e2c887f1 also optimize single-bit "$mux" cells in pass "opt_const", added suggestions 
for more optimizations
 2013-03-18 22:05:21 +01:00
Johann Glaser 15ad2db8fc fixed a crash when lines start with whitespace 2013-03-18 20:58:47 +01:00
Johann Glaser 2192873daa added description of Makefile include files for build configuration 2013-03-18 19:26:35 +01:00
Clifford Wolf 71de666003 More TODOs in README 2013-03-18 15:05:15 +01:00
Clifford Wolf bc5489f7ec Merge branch 'hansi' 2013-03-18 07:33:53 +01:00
Clifford Wolf 020a35d11e Removed date from auto-generated passes/techmap/stdcells.inc 2013-03-18 07:32:33 +01:00
Clifford Wolf 52914c2e68 Fixed abc eeror handling 2013-03-18 07:31:59 +01:00
Johann Glaser 3b8ebd694d add header to autogenerated file on its origin 2013-03-18 07:28:31 +01:00
Johann Glaser cd8008bda0 fixed typos 2013-03-18 07:28:31 +01:00
Clifford Wolf ba3793b642 Fixed strerrno vs. strerror types in ABC pass 2013-03-17 09:28:58 +01:00
Clifford Wolf 0133a98b73 Merge branch 'hansi' 2013-03-17 09:18:00 +01:00
Clifford Wolf 1390de4b74 Cleaned up ABC file/io error handling 2013-03-17 09:17:18 +01:00
Clifford Wolf e6cbeb5b16 Set execute bit on tests/openmsp430/run-synth.sh for real 2013-03-17 09:10:09 +01:00
Johann Glaser 0cb4a5936f added error checking at execution of ABC 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:06:03 +01:00
Johann Glaser fb494d4dd7 corrected typos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:06:02 +01:00
Johann Glaser a6f004e6f8 set executable flags to run-synth.sh, added .gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:06:02 +01:00
Johann Glaser 3cfbc18601 added ckeck for Icarus Verilog, otherwise the tests are silently stopped 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:05:15 +01:00
Johann Glaser bcae4aae6e corrected typos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:05:14 +01:00
Clifford Wolf 35b4a2c553 Fixed gcc warnings and added error handling to shell escape 2013-03-15 10:29:25 +01:00
Clifford Wolf cd5767d61b Added scc pass (find logic loops) 2013-03-15 10:24:08 +01:00
Clifford Wolf 13b2279b6c Added vi .*.swp files to .gitignore 2013-03-15 10:23:53 +01:00
Clifford Wolf 10956cb84a Added [[CITE]] tags to abc and fsm_extract passes 2013-03-15 10:23:02 +01:00
Clifford Wolf 89f009d171 Added additional functionality and cleanups in sigtools.h and celltypes.h 2013-03-15 10:22:23 +01:00
Clifford Wolf 3377a04bf2 Changed prefix for selection operators from # to % 2013-03-14 16:15:24 +01:00
Clifford Wolf 697cf1eb80 Added #ci and #co selection operators 2013-03-14 15:57:47 +01:00
Clifford Wolf b35add5f8c Added more features to #x selection operator 2013-03-14 15:35:05 +01:00
Clifford Wolf b0f386751c Added "select -write" command 2013-03-14 13:02:10 +01:00
Clifford Wolf 11789db206 More support code for $sr cells 2013-03-14 11:15:00 +01:00
Clifford Wolf de823ce964 Added $sr cell type to celltypes.h 2013-03-14 01:08:30 +01:00
Clifford Wolf 55f927eecb Fixed detection of public wires in opt_rmunused 2013-03-10 14:20:03 +01:00
Clifford Wolf eadf73c823 Added shell escape to command language 2013-03-10 14:05:42 +01:00
Clifford Wolf 0be19f6ca7 Fixed and improved #x selection operator 2013-03-08 10:15:15 +01:00
Clifford Wolf b96ffed69b Automatically select new objects in abc and techmap passes 2013-03-08 09:16:25 +01:00
Clifford Wolf 79b3afa011 Added ## selection operator (union all on stack) 2013-03-08 08:47:35 +01:00
Clifford Wolf 653f0049a8 Added select -count mode 2013-03-08 08:31:12 +01:00