Clifford Wolf
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947bd9b96b
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Renamed extend_un0() to extend_u0() and use it in genrtlil
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2013-11-07 18:17:10 +01:00 |
Clifford Wolf
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0e1661f84e
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Fixed type of sign extension in opt_const $eq/$ne handling
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2013-11-07 16:53:28 +01:00 |
Clifford Wolf
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f94266bb42
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Added eval -vloghammer_report mode
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2013-11-06 04:14:56 +01:00 |
Clifford Wolf
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8e8f1994b8
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Changed NEW_WIRE API to return the wire, not the signal
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2013-10-18 14:19:45 +02:00 |
Clifford Wolf
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cc5e379eca
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Added RTLIL NEW_WIRE macro
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2013-10-18 13:25:24 +02:00 |
Clifford Wolf
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0f38008ed3
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Added "design" command (-reset, -save, -load)
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2013-07-27 14:27:51 +02:00 |
Clifford Wolf
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21e38bed98
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Added "eval" pass
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2013-06-19 09:30:37 +02:00 |
Clifford Wolf
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6971c4db62
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Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
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2013-06-18 17:11:13 +02:00 |
Clifford Wolf
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21d9251e52
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Added "dump" command (part ilang backend)
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2013-06-02 17:53:30 +02:00 |
Clifford Wolf
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88af5b6a16
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Improved opt_share for reduce cells
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2013-03-29 11:19:21 +01:00 |
Clifford Wolf
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041c06bd9d
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Create nice errors when calling RTLIL::Module::derive() of base class
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2013-03-26 19:27:49 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |