yosys

Commit Graph

Author	SHA1	Message	Date
Catherine	1159e48721	write_verilog: emit `initial $display` correctly.	2024-01-11 13:13:04 +01:00
Charlotte	f9d38253c5	ast: add `PRIORITY` to `$print` cells	2023-08-11 04:46:52 +02:00
Charlotte	843ad9331b	cxxrtl: WIP: adjust comb display cells to only fire on change Naming and use of statics to be possibly revised.	2023-08-11 04:46:52 +02:00
Charlotte	7f7c61c9f0	fmt: remove lzero by lowering during Verilog parse See https://github.com/YosysHQ/yosys/pull/3721#issuecomment-1502037466 -- this reduces logic within the cell, and makes the rules that apply much more clear.	2023-08-11 04:46:52 +02:00
Charlotte	c391ee7a0d	docs: document simulation time format specifiers	2023-08-11 04:46:52 +02:00
Charlotte	202c3776e2	docs: elaborate $print documentation	2023-08-11 04:46:52 +02:00
Charlotte	2d7b8f71cc	docs: first pass $print documentation	2023-08-11 04:46:52 +02:00
Charlotte	0c0171bd60	docs: RD_DATA is an output, not input	2023-06-21 17:21:04 +10:00
Krystine Sherwin	d1b86d2fcf	docs: reflow memory map Move additional notes up to the top and give it its own section. Also reformat some paragraphs, and turn some bullet points into paragraphs. Split supported patterns section into some kind of grouping. Currently: - SDP - single-port RAM - reset patterns - asymmetric - TDP	2023-06-19 12:05:51 +12:00
Krystine Sherwin	3aee765793	Initial version of memory mapping doc	2023-05-26 09:36:01 +12:00
KrystalDelusion	b9b5899cce	Remove docs dependency on yosys repo (#3558 ) * Copies guidelines files into docs/ for website * Copying manual/CHAPTER_Prog for new docs * Copying manual/APPNOTE_011... for new docs Also adding faketime to list of packages for website build. Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com>	2022-11-24 15:56:44 +01:00
KrystalDelusion	a14dec79eb	Rst docs conversion (#3496 ) Rst docs conversion	2022-11-15 12:55:22 +01:00

12 Commits