riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,555 Commits 87 Branches 48 Tags 38 MiB
Commit Graph

10555 Commits

Author SHA1 Message Date
whitequark e4aa8bc96b cxxrtl: don't overwrite buffered inputs. 
Before this commit, a cell's input was always assigned like:

    p_cell.p_input = (value...);

If `p_input` is buffered (e.g. if the design is built at -O0), this
is not correct. (In practice, this breaks clocking.) Unfortunately,
the incorrect design was compiled without diagnostics because wire<>
was move-assignable and also implicitly constructible from value<>.

After this commit, cell inputs are no longer incorrectly assumed to
always be unbuffered, and wires are not assignable from values.
 2020-12-11 23:32:06 +00:00
Yosys Bot 442d19f647 Bump version 2020-12-10 00:10:10 +00:00
Miodrag Milanović 08510d7248
Merge pull request #2483 from YosysHQ/pmgen_nice_error 
Return nice error in pmgen generated code, fixes #2482
 2020-12-09 11:19:30 +01:00
Miodrag Milanovic 82dcf78cd9 Return nice error in pmgen generated code, fixes #2482 2020-12-09 11:06:22 +01:00
Yosys Bot c46452221e Bump version 2020-12-09 00:10:04 +00:00
David Shah f5cc1224f9 nexus: Add MULTADDSUB9X9WIDE sim model 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-08 15:49:20 +00:00
whitequark ec410c9b19
Merge pull request #2478 from whitequark/improve-bugpoint 
bugpoint: various improvements
 2020-12-08 07:32:11 +00:00
Zachary Snow 186d6df4c3 Allow constant function calls in constant function arguments 2020-12-07 13:53:27 -07:00
David Shah 17812a1560 nexus: Add LRAM inference 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-07 13:27:17 +00:00
whitequark 1838edf35c bugpoint: add -wires option. 2020-12-07 09:24:35 +00:00
whitequark 2b474a01e1 bugpoint: try to remove whole processes first. 2020-12-07 08:42:54 +00:00
whitequark b1135a88dd bugpoint: accept quoted strings in -grep. 2020-12-07 08:42:54 +00:00
whitequark 75f9e9cb45 bugpoint: add -command option. 2020-12-07 08:42:54 +00:00
Yosys Bot 95c6086681 Bump version 2020-12-04 00:10:06 +00:00
whitequark 13a270555b
Merge pull request #2470 from whitequark/cxxrtl-create_at 
cxxrtl: allow customizing the root module path in the C API
 2020-12-03 02:35:23 +00:00
whitequark e89f6ae819 cxxrtl: allow customizing the root module path in the C API. 2020-12-03 01:58:02 +00:00
Yosys Bot 5a15307926 Bump version 2020-12-03 00:10:09 +00:00
whitequark 3e13cfe53d
Merge pull request #2468 from whitequark/cxxrtl-assert 
cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert
 2020-12-02 23:36:22 +00:00
whitequark 3cb109f54b
Merge pull request #2469 from whitequark/cxxrtl-no-clk 
cxxrtl: fix crashes caused by a floating or constant clock input
 2020-12-02 23:36:03 +00:00
whitequark 98f7b435b0
Merge pull request #2466 from whitequark/cxxrtl-reset 
cxxrtl: provide a way to perform unobtrusive power-on reset
 2020-12-02 23:35:54 +00:00
whitequark 90724ea9e7
Merge pull request #2456 from Zottel/master 
Return correct modname when found in cache.
 2020-12-02 22:20:02 +00:00
whitequark 975b2d4283
Merge pull request #2455 from gsomlo/gls-fedpkg-fixes 
Fixes for building Fedora distro RPMs of yosys
 2020-12-02 22:19:52 +00:00
David Shah c3eb346e1e
Merge pull request #2467 from YosysHQ/dave/nexus-carry-fix 
nexus: More efficient CO mapping
 2020-12-02 22:07:25 +00:00
whitequark 7067f0d788 cxxrtl: fix crashes caused by a floating or constant clock input. 
E.g. in:

    module test;
        wire clk = 0;
        reg data;
        always @(posedge clk)
            data <= 0;
    endmodule
 2020-12-02 21:43:25 +00:00
whitequark 2945e27020
Merge pull request #2446 from RobertBaruch/rtlil_format 
Adds appendix on RTLIL text format
 2020-12-02 19:50:51 +00:00
whitequark aa0a15a42c cxxrtl: use CXXRTL_ASSERT for RTL contract violations instead of assert. 
RTL contract violations and C++ contract violations are different:
the former depend on the netlist and will never violate memory safety
whereas the latter may. When loading a CXXRTL simulation into another
process, RTL contract violations should generally not crash it, while
C++ contract violations should.
 2020-12-02 19:41:00 +00:00
David Shah 264e924abb nexus: More efficient CO mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2020-12-02 17:08:39 +00:00
Miodrag Milanovic 1c4a18f66f Bump required Verific version 2020-12-02 15:18:04 +01:00
whitequark 5beab5bc17 cxxrtl: provide a way to perform unobtrusive power-on reset. 
Although it is always possible to destroy and recreate the design to
simulate a power-on reset, this has two drawbacks:
  * Black boxes are also destroyed and recreated, which causes them
    to reacquire their resources, which might be costly and/or erase
    important state.
  * Pointers into the design are invalidated and have to be acquired
    again, which is costly and might be very inconvenient if they are
    captured elsewhere (especially through the C API).
 2020-12-02 08:25:27 +00:00
Yosys Bot d021f4b400 Bump version 2020-12-02 00:10:06 +00:00
Claire Xen 7b0cfd5c36
Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines 
Fix SYNTHESIS always being defined in Verilog frontend
 2020-12-01 12:31:34 +01:00
Miodrag Milanović ef5b2777c3
Merge pull request #2460 from pepijndevos/simple-gowin 
add -noalu and -json option for apicula
 2020-12-01 09:18:37 +01:00
georgerennie c1f6ce8b33 Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
Pepijn de Vos f155826a70 add -noalu and -json option for apicula 2020-11-30 11:43:12 +01:00
Julius Roob 2e23dfd96b Return correct modname when found in cache. 2020-11-26 13:31:22 +01:00
Gabriel Somlo 6a328e7032 fixup over commit 829b5cca to re-enable ABCEXTERNAL support 2020-11-26 06:12:12 -05:00
Gabriel Somlo 150b729b6f Add #include needed to build with gcc-11 
Suggested by Jeff Law <law@redhat.com>
 2020-11-26 06:12:12 -05:00
Yosys Bot 2116c58581 Bump version 2020-11-26 00:10:09 +00:00
whitequark 45725d3bdf
Merge pull request #2452 from whitequark/rtlil-remove-dot-identifiers 
rtlil: remove dotted identifiers
 2020-11-25 21:22:14 +00:00
Robert Baruch 2bb3fc654a Further juggles the wording of "character". 2020-11-25 12:02:35 -08:00
Robert Baruch 5d1bb79895 Clarifies how character encodings work. 2020-11-25 11:57:17 -08:00
Miodrag Milanović 180a8e5a45
Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments 
Generate only simple assignments in verilog backend
 2020-11-25 19:15:11 +01:00
Robert Baruch 1faf0e6dcc Clarifies whitespace and eol. 2020-11-25 10:06:22 -08:00
Robert Baruch 5615c41907 Cleans up doublequotes 2020-11-25 09:58:36 -08:00
Robert Baruch 09f6e9d6b6 Clarifies use of integers, and character set. 2020-11-25 09:53:39 -08:00
Miodrag Milanovic 7b093dca10 Add verilog backend option for simple_lhs 2020-11-25 18:21:41 +01:00
Robert Baruch 39af3e629f Clarifies processes, corrects some attributes 2020-11-25 08:59:25 -08:00
whitequark 015b476e56 rtlil: remove dotted identifiers. 
No one knows where they came from and they never did anything useful.
 2020-11-25 16:47:20 +00:00
Miodrag Milanovic addc493e8d generate only simple assignments in verilog backend 2020-11-25 17:43:28 +01:00
Claire Xen cf67e6a397
Merge pull request #2133 from dh73/nodev_head 
Adding latch tests for shift&mask AST dynamic part-select enhancements
 2020-11-25 09:44:23 +01:00