Miodrag Milanovic
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ea0b6258ab
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Simulation model verilog fix
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2019-06-26 18:34:34 +02:00 |
Eddie Hung
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efd04880db
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Add RAM32X1D support
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2019-06-24 16:16:50 -07:00 |
Eddie Hung
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13ad19482f
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Merge remote-tracking branch 'origin' into xc7srl
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2019-04-20 10:41:43 -07:00 |
Keith Rothman
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1f9235ede5
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Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-12 09:35:15 -07:00 |
Keith Rothman
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e107ccdde8
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Fix LUT6_2 definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-09 11:43:19 -07:00 |
Keith Rothman
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5e0339855f
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Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-04-09 09:01:53 -07:00 |
Eddie Hung
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f1a8e8a480
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Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-14 08:59:19 -07:00 |
Keith Rothman
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3e16f75bc6
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Revert FF models to include IS_x_INVERTED parameters.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 14:41:21 -08:00 |
Keith Rothman
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3090951d54
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Changes required for VPR place and route synth_xilinx.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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2019-03-01 12:02:27 -08:00 |
Eddie Hung
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73ddab6960
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Add SRL16 and SRL32 sim models
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2019-02-28 13:56:22 -08:00 |
Clifford Wolf
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6991c132b5
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Add Xilinx RAM64X1D and RAM128X1D simulation models
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2018-03-07 17:31:48 +01:00 |
Clifford Wolf
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853e949c0e
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Disabled (unused) Xilinx tristate buffers
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2015-02-04 16:33:59 +01:00 |
Clifford Wolf
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816fe6bbe0
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Added Xilinx example for Basys3 board
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2015-02-01 17:09:34 +01:00 |
Clifford Wolf
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909a95182b
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Fixed xilinx FDSE sim model
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2015-01-24 11:03:22 +01:00 |
Clifford Wolf
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7031231145
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Added MUXCY and XORCY support to synth_xilinx
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2015-01-17 15:39:54 +01:00 |
Clifford Wolf
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fd8c8d4fd3
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Added FF cells to xilinx/cells_sim.v
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2015-01-16 14:59:40 +01:00 |
Clifford Wolf
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38dfc5c580
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added minimalistic xilinx sim models
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2015-01-08 00:05:11 +01:00 |