- Use `:file:` role for file names, as well as `:makevar:` and `:program:`.
- Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets.
- Add link to ABC.
- More (and better) links to code examples. Formatted `:file:` text with link
to source on github.
- Includes a few extra todos (mostly picking up inline code blocks and a couple
intro reminders).
- Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags.
- Reflowing some paragraphs for spacing/width.
Filling out the hardware mapping sections, and actually highlighting the changes in schematics instead of just the memory block.
Also includes Part 4 of the coarse-grain rep, looking at `memory_collect` and putting the `synth_ice40 -top fifo -run :map_ram` command in its own (sub)section.
Includes a `no_rw_check` section label in `memory.rst` for reference (because I can't remember how to reference by heading).
Not sure about the opt output after map_ram section which has an open TODO, and the final steps section is also still open.
Blocking tasks are now capital TODO (compared to non-blocking todo).
Updated some of the todos.
Added note about which intel synth does which families.
Rename extended Yosys universe to Yosys family.
Added brief text to landing page, and also a note about the restructure and where to find old docs.
Moved todolist above ToC in preparation for disabling it in the config (so that it doesn't need it's own header).
Fixed pdf build, was previously breaking on trying to include the svg badges.
Moved remaining content into relevant places.
Added `load_design.rst` to more scripting.
Split fsm handling and abc out of optimization passes. Also moved things around to match the general flow previously described.
Changed generic `synth` for `prep` instead.
Krystine Sherwin